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https://github.com/trezor/trezor-firmware.git
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feat(core): allow for model R in firmware build
As model R will run on the same computational hardware as model T, memory_R.ld is just a symbolic link to memory_T.ld. [no changelog]
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@ -26,13 +26,13 @@ g_header:
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. = . + 8 // reserved
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. = . + 512 // hash1 ... hash16
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#if defined TREZOR_MODEL_T
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// model T header specifics
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#if !defined TREZOR_MODEL_1
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// trezor-core header style
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. = . + 415 // reserved
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.byte 0 // sigmask
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. = . + 64 // sig
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#elif defined TREZOR_MODEL_1
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// model 1 header specifics
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#else
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// model 1 compatibility header
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. = . + 64 // sig1
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. = . + 64 // sig2
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. = . + 64 // sig3
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@ -41,8 +41,6 @@ g_header:
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.byte 0 // sigindex3
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. = . + 220 // reserved
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. = . + 65 // reserved
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#else
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#error Unknown Trezor model
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#endif
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g_header_end:
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@ -65,7 +65,7 @@ int main(void) {
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#endif
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// reinitialize HAL for Trezor One
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#if defined TREZOR_MODEL_1
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#if defined TREZOR_MODEL_1 || defined TREZOR_MODEL_R
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HAL_Init();
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#endif
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@ -86,7 +86,7 @@ int main(void) {
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// Init peripherals
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pendsv_init();
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#if defined TREZOR_MODEL_1
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#if defined TREZOR_MODEL_1 || defined TREZOR_MODEL_R
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display_init();
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button_init();
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#endif
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1
core/embed/firmware/memory_R.ld
Symbolic link
1
core/embed/firmware/memory_R.ld
Symbolic link
@ -0,0 +1 @@
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memory_T.ld
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@ -48,7 +48,7 @@ reset_handler:
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// according to "ARM Cortex-M Programming Guide to Memory Barrier Instructions" Application Note 321, section 4.7:
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// "If it is not necessary to ensure that a pended interrupt is recognized immediately before
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// subsequent operations, it is not necessary to insert a memory barrier instruction."
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#if defined TREZOR_MODEL_T
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#if defined TREZOR_MODEL_T || defined TREZOR_MODEL_R
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cpsie f
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#elif defined TREZOR_MODEL_1
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cpsie if
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