15 Commits

Author	SHA1	Message	Date
tychovrahe	0f0f54f185	feat(core): support optiga on T3W1 ... [no changelog]	2024-11-20 11:17:35 +01:00
tychovrahe	c5b3dd72b9	feat(core): add support for SBU on T3W1 ... [no changelog]	2024-11-20 11:17:35 +01:00
tychovrahe	40c5426717	fix(core): fix MPU kernel sram setting for STM32U5G ... [no changelog]	2024-11-20 11:17:35 +01:00
tychovrahe	b4c95f4c16	fix(core): fix systick frequency computation by utilizing HSE_VALUE properly ... [no changelog]	2024-11-20 11:17:35 +01:00
tychovrahe	10687e8fa0	feat(core): add power button to T3W1 board rev A ... [no changelog]	2024-11-20 11:17:35 +01:00
cepetr	089db2cadf	refactor(core): restructure embed folder ... [no changelog]	2024-11-18 09:41:02 +01:00
tychovrahe	aac3559453	chore(core): move storage sectors to end of flash on U5G models ... [no changelog]	2024-11-14 09:30:20 +01:00
tychovrahe	fa953d7296	chore(core): switch T3W1 support to U5 ... [no changelog]	2024-11-14 09:30:20 +01:00
tychovrahe	435fbd6e8c	feat(core): add power button to button driver ... [no changelog]	2024-11-07 08:48:21 +01:00
cepetr	80a67c647f	refactor(core): relocate display resolution to model.h ... [no changelog]	2024-11-04 14:05:37 +01:00
cepetr	cb2c85dc2e	refactor(core): remove unused MAX_DISPLAY_RESx ... [no changelog]	2024-11-04 14:05:37 +01:00
tychovrahe	42396dd007	refactor(core): make USE_xxx defines global ... [no changelog]	2024-10-31 10:27:08 +01:00
cepetr	7bd3663930	fix(core): align coreapp start to 8KB (u5 only) ... [no changelog]	2024-10-31 10:25:31 +01:00
tychovrahe	d71d9e9c34	feat(core): add T3W1 emulator build ... [no changelog]	2024-10-09 15:06:40 +02:00
tychovrahe	915d4fca94	feat(core): add support for T3W1, on F4 ... [no changelog]	2024-10-09 15:06:40 +02:00