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fix(core): align coreapp start to 8KB (u5 only)

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This commit is contained in:
cepetr 2024-10-31 09:23:37 +01:00 committed by cepetr
parent c300576d6c
commit 7bd3663930
19 changed files with 45 additions and 30 deletions
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2
core/embed/lib/image.h
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@ -39,8 +39,6 @@
#define IMAGE_CODE_ALIGN(addr) \
((((uint32_t)(uintptr_t)addr) + (CODE_ALIGNMENT - 1)) & ~(CODE_ALIGNMENT - 1))
#define COREAPP_ALIGNMENT 512
#define COREAPP_CODE_ALIGN(addr) \
((((uint32_t)(uintptr_t)addr) + (COREAPP_ALIGNMENT - 1)) & \
~(COREAPP_ALIGNMENT - 1))

1
core/embed/models/D001/memory.ld
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@ -50,3 +50,4 @@ KERNEL_FRAMEBUFFER_SIZE = 0x0;
KERNEL_SRAM_SIZE = 0x400;
BOOTARGS_SIZE = 0x100;
CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x200;

9
core/embed/models/D001/model_D001.h
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@ -87,12 +87,13 @@
#define FIRMWARE_P2_SECTOR_END 23
// RAM layout
#define KERNEL_STACK_SIZE 8 * 1024
#define KERNEL_CCMRAM_SIZE 16 * 1024
#define KERNEL_FRAMEBUFFER_SIZE 0 * 1024
#define KERNEL_SRAM_SIZE 1 * 1024
#define KERNEL_STACK_SIZE (8 * 1024)
#define KERNEL_CCMRAM_SIZE (16 * 1024)
#define KERNEL_FRAMEBUFFER_SIZE (0 * 1024)
#define KERNEL_SRAM_SIZE (1 * 1024)
#define BOOTARGS_SIZE 0x100
#define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x200
#endif

1
core/embed/models/D002/memory.ld
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@ -45,3 +45,4 @@ KERNEL_SRAM2_SIZE = 0x2400;
KERNEL_SRAM3_SIZE = 0xbb800;
BOOTARGS_SIZE = 0x100;
CODE_ALIGNMENT = 0x400;
COREAPP_ALIGNMENT = 0x2000;

7
core/embed/models/D002/model_D002.h
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@ -83,11 +83,12 @@
// RAM layout
#define KERNEL_U_RAM_SIZE 512
#define KERNEL_SRAM1_SIZE 16 * 1024
#define KERNEL_SRAM2_SIZE 9 * 1024
#define KERNEL_SRAM3_SIZE 750 * 1024
#define KERNEL_SRAM1_SIZE (16 * 1024)
#define KERNEL_SRAM2_SIZE (9 * 1024)
#define KERNEL_SRAM3_SIZE (750 * 1024)
#define BOOTARGS_SIZE 0x100
#define CODE_ALIGNMENT 0x400
#define COREAPP_ALIGNMENT 0x2000
#endif

1
core/embed/models/T2B1/memory.ld
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@ -54,3 +54,4 @@ KERNEL_FRAMEBUFFER_SIZE = 0x2000;
KERNEL_SRAM_SIZE = 0x400;
BOOTARGS_SIZE = 0x100;
CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x200;

9
core/embed/models/T2B1/model_T2B1.h
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@ -92,12 +92,13 @@
#define FIRMWARE_P2_SECTOR_END 23
// RAM layout
#define KERNEL_STACK_SIZE 8 * 1024
#define KERNEL_CCMRAM_SIZE 16 * 1024
#define KERNEL_FRAMEBUFFER_SIZE 8 * 1024
#define KERNEL_SRAM_SIZE 1 * 1024
#define KERNEL_STACK_SIZE (8 * 1024)
#define KERNEL_CCMRAM_SIZE (16 * 1024)
#define KERNEL_FRAMEBUFFER_SIZE (8 * 1024)
#define KERNEL_SRAM_SIZE (1 * 1024)
#define BOOTARGS_SIZE 0x100
#define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x200
#endif

1
core/embed/models/T2T1/memory.ld
View File

@ -50,3 +50,4 @@ KERNEL_FRAMEBUFFER_SIZE = 0x0;
KERNEL_SRAM_SIZE = 0x400;
BOOTARGS_SIZE = 0x100;
CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x200;

9
core/embed/models/T2T1/model_T2T1.h
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@ -87,12 +87,13 @@
#define FIRMWARE_P2_SECTOR_END 23
// RAM layout
#define KERNEL_STACK_SIZE 8 * 1024
#define KERNEL_CCMRAM_SIZE 16 * 1024
#define KERNEL_FRAMEBUFFER_SIZE 0 * 1024
#define KERNEL_SRAM_SIZE 1 * 1024
#define KERNEL_STACK_SIZE (8 * 1024)
#define KERNEL_CCMRAM_SIZE (16 * 1024)
#define KERNEL_FRAMEBUFFER_SIZE (0 * 1024)
#define KERNEL_SRAM_SIZE (1 * 1024)
#define BOOTARGS_SIZE 0x100
#define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x200
#endif

1
core/embed/models/T3B1/memory.ld
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@ -45,3 +45,4 @@ KERNEL_SRAM2_SIZE = 0x2000;
KERNEL_SRAM3_SIZE = 0x38400;
BOOTARGS_SIZE = 0x100;
CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x2000;

5
core/embed/models/T3B1/model_T3B1.h
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@ -82,11 +82,12 @@
// RAM layout
#define KERNEL_U_RAM_SIZE 512
#define KERNEL_SRAM1_SIZE 16 * 1024
#define KERNEL_SRAM2_SIZE 8 * 1024
#define KERNEL_SRAM1_SIZE (16 * 1024)
#define KERNEL_SRAM2_SIZE (8 * 1024)
#define KERNEL_SRAM3_SIZE 0x38400
#define BOOTARGS_SIZE 0x100
#define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x2000
#endif

1
core/embed/models/T3T1/memory.ld
View File

@ -45,3 +45,4 @@ KERNEL_SRAM2_SIZE = 0x2000;
KERNEL_SRAM3_SIZE = 0x38400;
BOOTARGS_SIZE = 0x100;
CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x2000;

5
core/embed/models/T3T1/model_T3T1.h
View File

@ -82,11 +82,12 @@
// RAM layout
#define KERNEL_U_RAM_SIZE 512
#define KERNEL_SRAM1_SIZE 16 * 1024
#define KERNEL_SRAM2_SIZE 8 * 1024
#define KERNEL_SRAM1_SIZE (16 * 1024)
#define KERNEL_SRAM2_SIZE (8 * 1024)
#define KERNEL_SRAM3_SIZE 0x38400
#define BOOTARGS_SIZE 0x100
#define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x2000
#endif

1
core/embed/models/T3W1/memory.ld
View File

@ -50,3 +50,4 @@ KERNEL_FRAMEBUFFER_SIZE = 0x0;
KERNEL_SRAM_SIZE = 0x400;
BOOTARGS_SIZE = 0x100;
CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x2000;

10
core/embed/models/T3W1/model_T3W1.h
View File

@ -89,11 +89,13 @@
#define FIRMWARE_P2_SECTOR_END 23
// RAM layout
#define KERNEL_STACK_SIZE 8 * 1024
#define KERNEL_CCMRAM_SIZE 16 * 1024
#define KERNEL_FRAMEBUFFER_SIZE 0 * 1024
#define KERNEL_SRAM_SIZE 1 * 1024
#define KERNEL_STACK_SIZE (8 * 1024)
#define KERNEL_CCMRAM_SIZE (16 * 1024)
#define KERNEL_FRAMEBUFFER_SIZE (0 * 1024)
#define KERNEL_SRAM_SIZE (1 * 1024)
#define BOOTARGS_SIZE 0x100
#define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x2000
#endif

2
core/embed/trezorhal/stm32f4/linker/firmware.ld
View File

@ -52,7 +52,7 @@ SECTIONS {
.flash : ALIGN(512) {
KEEP(*(.kernel));
. = ALIGN(512);
. = ALIGN(COREAPP_ALIGNMENT);
KEEP(*(.vector_table));
. = ALIGN(4);
*(.text*);

2
core/embed/trezorhal/stm32u5/linker/u58/firmware.ld
View File

@ -47,7 +47,7 @@ SECTIONS {
.flash : ALIGN(CODE_ALIGNMENT) {
KEEP(*(.kernel));
. = ALIGN(512);
. = ALIGN(COREAPP_ALIGNMENT);
KEEP(*(.vector_table));
. = ALIGN(4);
*(.text*);

2
core/embed/trezorhal/stm32u5/linker/u5a/firmware.ld
View File

@ -46,7 +46,7 @@ SECTIONS {
.flash : ALIGN(CODE_ALIGNMENT) {
KEEP(*(.kernel));
. = ALIGN(512);
. = ALIGN(COREAPP_ALIGNMENT);
KEEP(*(.vector_table));
. = ALIGN(4);
*(.text*);

6
core/embed/trezorhal/stm32u5/mpu.c
View File

@ -21,6 +21,7 @@
#include <stdbool.h>
#include "common.h"
#include "image.h"
#include "irq.h"
#include "model.h"
#include "mpu.h"
@ -172,8 +173,9 @@ extern uint32_t _codelen;
#define KERNEL_FLASH_START KERNEL_START
#define KERNEL_FLASH_SIZE (KERNEL_SIZE - KERNEL_U_FLASH_SIZE)
#define COREAPP_FLASH_START (KERNEL_FLASH_START + KERNEL_SIZE)
#define COREAPP_FLASH_SIZE (FIRMWARE_MAXSIZE - KERNEL_SIZE)
#define COREAPP_FLASH_START COREAPP_CODE_ALIGN(KERNEL_FLASH_START + KERNEL_SIZE)
#define COREAPP_FLASH_SIZE \
(FIRMWARE_MAXSIZE - (COREAPP_FLASH_START - KERNEL_FLASH_START))
#ifdef STM32U585xx
#define COREAPP_RAM1_START SRAM1_BASE