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Commit Graph

83 Commits

Author SHA1 Message Date
Tomas Susanka
cec1f39a90 chore(core, legacy): bump versions 
[no changelog]
 2021-08-31 12:55:37 +02:00
Martin Milata
81869fc4b0 chore(core): bump version to 2.4.2 
[skip_ci]
 2021-07-08 13:38:29 +02:00
Ondřej Vejpustek
24200e7424 fixup! fix(legacy): make RDI work on T1 2021-06-24 17:34:24 +02:00
Ondrej Mikle
daa94ac941 fix(legacy): make RDI work on T1 2021-06-24 17:34:24 +02:00
Ondřej Vejpustek
4968d7da53 feat(core): implement svc shutdown 2021-06-23 16:40:45 +02:00
Ondřej Vejpustek
cca9d4b1c4 refactor(core): rename shutdown to shutdown_privileged 2021-06-23 16:40:45 +02:00
Ondřej Vejpustek
7686eb355a fix(core): fix import of random delays 2021-06-23 16:40:45 +02:00
Jan Pochyla
8a21e3fc73 feat(core): Add Rust Protobuf codec 2021-06-08 09:55:19 +02:00
Martin Milata
ca836b2e45 chore(core): bump version to 2.4.1 2021-06-02 12:50:22 +02:00
Martin Milata
8c6b93e0bd build(core): account for ARM unwinding info in memory layout 
Currently the 8-byte section is inserted under semi-random name like
.ARM.exidx.text._ZN50_$LT$T$u20$as$u20$core..convert..Into$LT$U$GT$$GT$4into17h79ccbc4bdfe3f200E.
This makes it hard to include it in _codelen that is later baked into
firmware header. This change adds new section because including it in
.flash causes linker error due to mixing "ordered" and "unordered"
sections.

By renaming .exidx to /DISCARD/ we'd drop this info, there may also
exist compiler flag to do that.
 2021-05-21 13:49:42 +02:00
Ondřej Vejpustek
6fd4739c5c feat(core): make random delays use chacha_drbg 2021-05-21 13:42:53 +02:00
Ondřej Vejpustek
8ee17f69b3 refactor(core): move wait_random and rdi into separate file 2021-05-21 13:42:53 +02:00
matejcik
5f4240d93c feat(core): preallocate sys.modules to an appropriate size 2021-05-06 13:14:21 +02:00
Jan Pochyla
6257584951 feat(core): Add Rust bindings to MicroPython and trezorhal 
core: Remove dangling module decls

core: Use new Cargo feature resolver, use external MacOS debug info

core: Rust docs improvements

core: Upgrade bindgen

core: Add test target to Rust

ci: build rust sources

build(core): .ARM.exidx.text.__aeabi_ui2f in t1 firmware size

It's an unwind table for softfloat function inserted by rustc, probably
can be removed to save 8 bytes:
599c58db70/link.x.in (L175-L182)

scons: Remove dead code

core: Move Rust target to build/rust

core: Replace extern with a FFI version

core: Add some explanatory Rust comments

core: Use correct path for the Rust lib

core: Remove Buffer::as_mut()

Mutable buffer access needs MP_BUFFER_WRITE flag. TBD in the Protobuf PR.

core: Improve docs for micropython::Buffer

core: Minor Rust docs changes

core: Rewrite trezor_obj_get_ll_checked

core: Fix incorrect doc comment

core: Remove cc from deps

fixup! core: Rewrite trezor_obj_get_ll_checked

core: update safety comments
 2021-05-05 16:00:21 +02:00
Andrew Kozlik
66823e2893 chore(core,legacy): Bump FIX_VERSIONs due to upgrade to storage version 3. 2021-03-25 14:24:41 +01:00
Pavol Rusnak
814db111b2
feat(core): add define to invert display colors on ST7789V 2021-03-10 16:06:18 +01:00
Pavol Rusnak
5395c542c1
chore(core): update changelog, bump version to 2.3.7 2021-02-13 11:16:11 +01:00
Pavol Rusnak
a11cb11ba3 chore(core): rework SYSTEMVIEW_DEST_SYSTEMVIEW 
to work with ifdef instead of if
 2021-01-26 20:53:38 +01:00
Ondrej Mikle
d99127771c chore(core): reorder includes 2021-01-26 20:53:38 +01:00
Ondrej Mikle
a628b9a92d chore(core): remove unneeded include 2021-01-26 20:53:38 +01:00
Ondrej Mikle
9411756c42 style(core): systemview reformat 2021-01-26 20:53:38 +01:00
Ondrej Mikle
550216354b chore(core): more systematic systemview function definitions 2021-01-26 20:53:38 +01:00
Ondrej Mikle
869cfbbd1c style(core): style for systemview 2021-01-26 20:53:38 +01:00
Ondrej Mikle
5f837e12b9 feat(core): send messaged through systemview 2021-01-26 20:53:38 +01:00
Ondrej Mikle
60e4e06aa5 feat(core): measure systick with systemview 2021-01-26 20:53:38 +01:00
Ondrej Mikle
c5e986b1ba feat(core): enable SystemView at firmware start 2021-01-26 20:53:38 +01:00
Tomas Susanka
1006c8a0f1 chore(core,legacy): change versions to 1.9.5 and 2.3.6 
This reverts commit 92535dc090.
 2021-01-22 15:42:55 +01:00
Pavol Rusnak
92535dc090
chore(core,legacy): change versions back to 1.9.4 and 2.3.5 
[skip_ci]
 2021-01-22 14:23:11 +01:00
Pavol Rusnak
43ed13b323 feat(core): disable SECP256K1_ZKP feature flag 2021-01-22 14:06:29 +01:00
Jan Pochyla
f3a64435f1
fix(core): root ui callback for trezorconfig mod (#1412) 
Co-authored-by: Pavol Rusnak <pavol@rusnak.io>
 2021-01-19 14:17:16 +01:00
Tomas Susanka
d2e3269ede chore(core): bump version to 2.3.6 2020-12-18 19:36:25 +01:00
Pavol Rusnak
0519c8bd13
Revert "chore(core): bump version to 2.3.6" 
This reverts commit 01d1058048.
 2020-11-26 16:48:47 +01:00
Tomas Susanka
01d1058048 chore(core): bump version to 2.3.6 2020-11-25 20:14:30 +01:00
Pavol Rusnak
50fdd183c2
ci: enable editorconfig checks, fix whitespace issues 2020-11-11 14:43:50 +01:00
Pavol Rusnak
ded61a4ccf
chore(vendor): update micropython to v1.13 2020-10-16 14:19:35 +02:00
Tomas Susanka
0317877297 chore(core): bump version to 2.3.5 2020-09-24 10:17:32 +02:00
Tomas Susanka
d080464cc5 core, legacy: bump versions (also in changelogs) 2020-08-24 09:31:49 +02:00
Pavol Rusnak
5536fbb98a python: use stdlib blake2s on python 3.6+ 
commit 6d407c84d7 did not replace everything
 2020-08-10 23:35:38 +02:00
Pavol Rusnak
efc5ccdaf0
core: remove src1 2020-08-03 15:59:57 +02:00
Pavol Rusnak
89d701ed08
core+legacy: bump versions (also in changelogs) 2020-07-27 13:59:49 +02:00
matejcik
f723dca7b1 core: enable PYSTACK 2020-07-24 14:09:31 +02:00
Andrew Kozlik
4005f4832f core/embed: Set VCP write timeout to 0. 2020-07-16 09:34:58 +02:00
Ondrej Mikle
33d2bf417b core: replace bootloader only in production. Fix device for T1 core port JLink upload 2020-07-13 10:45:32 +02:00
Pavol Rusnak
179645e3ad core: unify usage of TREZOR_MODEL 2020-06-06 21:06:15 +02:00
Tomas Susanka
8859d103f4 core, legacy: bump versions 2020-06-03 15:39:25 +00:00
Ondrej Mikle
b01b24f090 core: change startup firmware file from .s to .S which enables preprocessing and fixes TT boot 2020-05-24 12:28:38 +02:00
Ondrej Mikle
10f0f107e0 core: Adds T1 core port FW flashing options for for openocd and jlink 2020-05-21 10:05:12 +02:00
Ondrej Mikle
0d65d684f0 core: T1 port can run on T1 bootloader with MEMORY_PROTECT=0 2020-05-21 08:49:59 +02:00
Ondrej Mikle
7eddafe487 core: better formatting for common parts of T1 and TT header 2020-05-14 16:10:42 +02:00
Ondrej Mikle
c4c341b3f9 core: setup stack when running core on T1 2020-05-14 12:46:25 +02:00