Fix send sync bit update

M1nd3r/thp5
M1nd3r 2 months ago
parent 73a7bb788a
commit ad3b878625

@ -132,6 +132,7 @@ def _sync_set_send_bit(cache: SessionThpCache | ChannelCache, bit: int) -> None:
# set third bit to "bit" value
cache.sync &= 0xDF
if bit:
cache.sync |= 0x20

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