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fix(core): correct swapped F4/U5 reset flags
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@ -29,8 +29,9 @@ secbool reset_flags_check(void) {
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// for production. check the reset flags to assure that we arrive here due to
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// for production. check the reset flags to assure that we arrive here due to
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// a regular full power-on event, and not as a result of a lesser reset.
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// a regular full power-on event, and not as a result of a lesser reset.
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if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF |
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if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF |
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RCC_CSR_SFTRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF |
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RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF | RCC_CSR_PINRSTF |
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RCC_CSR_OBLRSTF)) != (RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) {
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RCC_CSR_BORRSTF)) !=
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(RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) {
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return secfalse;
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return secfalse;
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}
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}
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#endif
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#endif
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@ -29,9 +29,8 @@ secbool reset_flags_check(void) {
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// for production. check the reset flags to assure that we arrive here due to
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// for production. check the reset flags to assure that we arrive here due to
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// a regular full power-on event, and not as a result of a lesser reset.
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// a regular full power-on event, and not as a result of a lesser reset.
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if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF |
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if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF |
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RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF | RCC_CSR_PINRSTF |
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RCC_CSR_SFTRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF |
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RCC_CSR_BORRSTF)) !=
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RCC_CSR_OBLRSTF)) != (RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) {
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(RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) {
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return secfalse;
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return secfalse;
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}
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}
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#endif
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#endif
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