From 3a19609035c3597f21306c7e9134c5156f5ccd98 Mon Sep 17 00:00:00 2001 From: cepetr Date: Tue, 22 Oct 2024 22:07:45 +0200 Subject: [PATCH] fix(core): correct swapped F4/U5 reset flags [no changelog] --- core/embed/trezorhal/stm32f4/reset_flags.c | 5 +++-- core/embed/trezorhal/stm32u5/reset_flags.c | 5 ++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/core/embed/trezorhal/stm32f4/reset_flags.c b/core/embed/trezorhal/stm32f4/reset_flags.c index 675dc2dc54..ce4a664b93 100644 --- a/core/embed/trezorhal/stm32f4/reset_flags.c +++ b/core/embed/trezorhal/stm32f4/reset_flags.c @@ -29,8 +29,9 @@ secbool reset_flags_check(void) { // for production. check the reset flags to assure that we arrive here due to // a regular full power-on event, and not as a result of a lesser reset. if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | - RCC_CSR_SFTRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF | - RCC_CSR_OBLRSTF)) != (RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) { + RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | + RCC_CSR_BORRSTF)) != + (RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) { return secfalse; } #endif diff --git a/core/embed/trezorhal/stm32u5/reset_flags.c b/core/embed/trezorhal/stm32u5/reset_flags.c index ce4a664b93..675dc2dc54 100644 --- a/core/embed/trezorhal/stm32u5/reset_flags.c +++ b/core/embed/trezorhal/stm32u5/reset_flags.c @@ -29,9 +29,8 @@ secbool reset_flags_check(void) { // for production. check the reset flags to assure that we arrive here due to // a regular full power-on event, and not as a result of a lesser reset. if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF | - RCC_CSR_SFTRSTF | RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | - RCC_CSR_BORRSTF)) != - (RCC_CSR_PORRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) { + RCC_CSR_SFTRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF | + RCC_CSR_OBLRSTF)) != (RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) { return secfalse; } #endif