From 33bb7ef410ef450a37a2180d56708000a76854d3 Mon Sep 17 00:00:00 2001
From: tychovrahe <brunam@seznam.cz>
Date: Wed, 1 Jan 2025 12:23:59 +0100
Subject: [PATCH] fix(core): increase framebuffer section size on U5G models

[no changelog]
---
 core/embed/models/D002/memory.ld              | 16 ++++++++--------
 core/embed/models/D002/model_D002.h           | 18 +++++++++---------
 core/embed/models/T3W1/memory.ld              | 16 ++++++++--------
 core/embed/models/T3W1/model_T3W1.h           | 18 +++++++++---------
 core/embed/sys/linker/stm32u5g/boardloader.ld |  8 ++++----
 core/embed/sys/linker/stm32u5g/bootloader.ld  |  4 ++--
 core/embed/sys/linker/stm32u5g/kernel.ld      |  4 ++--
 core/embed/sys/linker/stm32u5g/prodtest.ld    |  4 ++--
 8 files changed, 44 insertions(+), 44 deletions(-)

diff --git a/core/embed/models/D002/memory.ld b/core/embed/models/D002/memory.ld
index 392840905d..58cc39ffd2 100644
--- a/core/embed/models/D002/memory.ld
+++ b/core/embed/models/D002/memory.ld
@@ -39,17 +39,17 @@ ASSETS_START = 0xc3e0000;
 ASSETS_MAXSIZE = 0x20000;
 ASSETS_SECTOR_START = 0x1f0;
 ASSETS_SECTOR_END = 0x1ff;
-FB1_RAM_START = 0x30000000;
-FB1_RAM_SIZE = 0xbfe00;
-BOOTARGS_START = 0x300bfe00;
+BOOTARGS_START = 0x30000000;
 BOOTARGS_SIZE = 0x200;
-MAIN_RAM_START = 0x300c0000;
-MAIN_RAM_SIZE = 0xfe00;
+FB1_RAM_START = 0x30000200;
+FB1_RAM_SIZE = 0xc1000;
+MAIN_RAM_START = 0x300c1200;
+MAIN_RAM_SIZE = 0xec00;
 SAES_RAM_START = 0x300cfe00;
 SAES_RAM_SIZE = 0x200;
 FB2_RAM_START = 0x300d0000;
-FB2_RAM_SIZE = 0xc0000;
-AUX1_RAM_START = 0x30190000;
-AUX1_RAM_SIZE = 0xe0000;
+FB2_RAM_SIZE = 0xc1000;
+AUX1_RAM_START = 0x30191000;
+AUX1_RAM_SIZE = 0xdf000;
 CODE_ALIGNMENT = 0x400;
 COREAPP_ALIGNMENT = 0x2000;
diff --git a/core/embed/models/D002/model_D002.h b/core/embed/models/D002/model_D002.h
index 6488416876..0fec46238a 100644
--- a/core/embed/models/D002/model_D002.h
+++ b/core/embed/models/D002/model_D002.h
@@ -85,23 +85,23 @@
 #define ASSETS_SECTOR_END 0x1FF
 
 // RAM layout
-#define FB1_RAM_START 0x30000000
-#define FB1_RAM_SIZE (768 * 1024 - 512)
-
-#define BOOTARGS_START 0x300BFE00
+#define BOOTARGS_START 0x30000000
 #define BOOTARGS_SIZE 0x200
 
-#define MAIN_RAM_START 0x300C0000
-#define MAIN_RAM_SIZE (64 * 1024 - 512)
+#define FB1_RAM_START 0x30000200
+#define FB1_RAM_SIZE (772 * 1024)
+
+#define MAIN_RAM_START 0x300C1200
+#define MAIN_RAM_SIZE (60 * 1024 - 512 - 512)
 
 #define SAES_RAM_START 0x300CFE00
 #define SAES_RAM_SIZE 512
 
 #define FB2_RAM_START 0x300D0000
-#define FB2_RAM_SIZE (768 * 1024)
+#define FB2_RAM_SIZE (772 * 1024)
 
-#define AUX1_RAM_START 0x30190000
-#define AUX1_RAM_SIZE (896 * 1024)
+#define AUX1_RAM_START 0x30191000
+#define AUX1_RAM_SIZE (892 * 1024)
 
 // misc
 #define CODE_ALIGNMENT 0x400
diff --git a/core/embed/models/T3W1/memory.ld b/core/embed/models/T3W1/memory.ld
index 392840905d..58cc39ffd2 100644
--- a/core/embed/models/T3W1/memory.ld
+++ b/core/embed/models/T3W1/memory.ld
@@ -39,17 +39,17 @@ ASSETS_START = 0xc3e0000;
 ASSETS_MAXSIZE = 0x20000;
 ASSETS_SECTOR_START = 0x1f0;
 ASSETS_SECTOR_END = 0x1ff;
-FB1_RAM_START = 0x30000000;
-FB1_RAM_SIZE = 0xbfe00;
-BOOTARGS_START = 0x300bfe00;
+BOOTARGS_START = 0x30000000;
 BOOTARGS_SIZE = 0x200;
-MAIN_RAM_START = 0x300c0000;
-MAIN_RAM_SIZE = 0xfe00;
+FB1_RAM_START = 0x30000200;
+FB1_RAM_SIZE = 0xc1000;
+MAIN_RAM_START = 0x300c1200;
+MAIN_RAM_SIZE = 0xec00;
 SAES_RAM_START = 0x300cfe00;
 SAES_RAM_SIZE = 0x200;
 FB2_RAM_START = 0x300d0000;
-FB2_RAM_SIZE = 0xc0000;
-AUX1_RAM_START = 0x30190000;
-AUX1_RAM_SIZE = 0xe0000;
+FB2_RAM_SIZE = 0xc1000;
+AUX1_RAM_START = 0x30191000;
+AUX1_RAM_SIZE = 0xdf000;
 CODE_ALIGNMENT = 0x400;
 COREAPP_ALIGNMENT = 0x2000;
diff --git a/core/embed/models/T3W1/model_T3W1.h b/core/embed/models/T3W1/model_T3W1.h
index 7a2f7f93d8..f9fd1146f4 100644
--- a/core/embed/models/T3W1/model_T3W1.h
+++ b/core/embed/models/T3W1/model_T3W1.h
@@ -91,23 +91,23 @@
 #define ASSETS_SECTOR_END 0x1FF
 
 // RAM layout
-#define FB1_RAM_START 0x30000000
-#define FB1_RAM_SIZE (768 * 1024 - 512)
-
-#define BOOTARGS_START 0x300BFE00
+#define BOOTARGS_START 0x30000000
 #define BOOTARGS_SIZE 0x200
 
-#define MAIN_RAM_START 0x300C0000
-#define MAIN_RAM_SIZE (64 * 1024 - 512)
+#define FB1_RAM_START 0x30000200
+#define FB1_RAM_SIZE (772 * 1024)
+
+#define MAIN_RAM_START 0x300C1200
+#define MAIN_RAM_SIZE (60 * 1024 - 512 - 512)
 
 #define SAES_RAM_START 0x300CFE00
 #define SAES_RAM_SIZE 512
 
 #define FB2_RAM_START 0x300D0000
-#define FB2_RAM_SIZE (768 * 1024)
+#define FB2_RAM_SIZE (772 * 1024)
 
-#define AUX1_RAM_START 0x30190000
-#define AUX1_RAM_SIZE (896 * 1024)
+#define AUX1_RAM_START 0x30191000
+#define AUX1_RAM_SIZE (892 * 1024)
 
 // misc
 #define CODE_ALIGNMENT 0x400
diff --git a/core/embed/sys/linker/stm32u5g/boardloader.ld b/core/embed/sys/linker/stm32u5g/boardloader.ld
index 390100db55..f9ec3c1610 100644
--- a/core/embed/sys/linker/stm32u5g/boardloader.ld
+++ b/core/embed/sys/linker/stm32u5g/boardloader.ld
@@ -31,16 +31,16 @@ confidential_vma = ADDR(.confidential);
 confidential_size = SIZEOF(.confidential);
 
 /* used by the startup code to wipe memory */
-_startup_clear_ram_0_start = MCU_SRAM1;
-_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
+_startup_clear_ram_0_start = MCU_SRAM1 + BOOTARGS_SIZE;
+_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
 _startup_clear_ram_1_start = MCU_SRAM2;
 _startup_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
 _startup_clear_ram_2_start = MCU_SRAM4;
 _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
 
 /* used by the jump code to wipe memory */
-_handoff_clear_ram_0_start = MCU_SRAM1;
-_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
+_handoff_clear_ram_0_start = MCU_SRAM1 + BOOTARGS_SIZE;
+_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
 _handoff_clear_ram_1_start = MCU_SRAM2;
 _handoff_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
 _handoff_clear_ram_2_start = MCU_SRAM4;
diff --git a/core/embed/sys/linker/stm32u5g/bootloader.ld b/core/embed/sys/linker/stm32u5g/bootloader.ld
index 5c7c277a6c..1a4a5f05a6 100644
--- a/core/embed/sys/linker/stm32u5g/bootloader.ld
+++ b/core/embed/sys/linker/stm32u5g/bootloader.ld
@@ -30,8 +30,8 @@ confidential_vma = ADDR(.confidential);
 confidential_size = SIZEOF(.confidential);
 
 /* used by the startup code to wipe memory */
-_startup_clear_ram_0_start = MCU_SRAM1;
-_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
+_startup_clear_ram_0_start = MCU_SRAM1 + BOOTARGS_SIZE;
+_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
 _startup_clear_ram_1_start = MCU_SRAM2;
 _startup_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
 _startup_clear_ram_2_start = MCU_SRAM4;
diff --git a/core/embed/sys/linker/stm32u5g/kernel.ld b/core/embed/sys/linker/stm32u5g/kernel.ld
index 22db253745..6ed802c874 100644
--- a/core/embed/sys/linker/stm32u5g/kernel.ld
+++ b/core/embed/sys/linker/stm32u5g/kernel.ld
@@ -41,8 +41,8 @@ _startup_clear_ram_2_start = MCU_SRAM4;
 _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
 
 /* used by the jump code to wipe memory */
-_handoff_clear_ram_0_start = MCU_SRAM1;
-_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
+_handoff_clear_ram_0_start = MCU_SRAM1 + BOOTARGS_SIZE;
+_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
 _handoff_clear_ram_1_start = MCU_SRAM2;
 _handoff_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
 _handoff_clear_ram_2_start = MCU_SRAM4;
diff --git a/core/embed/sys/linker/stm32u5g/prodtest.ld b/core/embed/sys/linker/stm32u5g/prodtest.ld
index a956e420f9..288899125d 100644
--- a/core/embed/sys/linker/stm32u5g/prodtest.ld
+++ b/core/embed/sys/linker/stm32u5g/prodtest.ld
@@ -38,8 +38,8 @@ _startup_clear_ram_2_start = MCU_SRAM4;
 _startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
 
 /* used by the jump code to wipe memory */
-_handoff_clear_ram_0_start = MCU_SRAM1;
-_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
+_handoff_clear_ram_0_start = MCU_SRAM1 + BOOTARGS_SIZE;
+_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
 _handoff_clear_ram_1_start = MCU_SRAM2;
 _handoff_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
 _handoff_clear_ram_2_start = MCU_SRAM4;