feat(core): allow access to translations area in firmware

[no changelog]
tychovrahe/fw_translations/mpu
tychovrahe 7 months ago
parent f46e7e65cb
commit 0f3e082e06

@ -101,110 +101,109 @@ void mpu_config_bootloader(void) {
} }
void mpu_config_firmware(void) { void mpu_config_firmware(void) {
// TODO: Michal said this should be commented, but even with return below // Disable MPU
// the hardware is not working (blank screen on TT) HAL_MPU_Disable();
// It has these warnings during the FW build:
// - warning: _popcountsi2.o: missing .note.GNU-stack section implies // Note: later entries overwrite previous ones
// executable stack
// - NOTE: This behaviour is deprecated and will be removed in a future /*
// version of the linker // Boardloader (0x08000000 - 0x0800FFFF, 64 KiB, read-only, execute never)
// - warning: build/firmware/firmware.elf has a LOAD segment with RWX MPU->RBAR = FLASH_BASE | MPU_REGION_NUMBER0;
// permissions MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// return; LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_PRIV_RO_URO | MPU_RASR_XN_Msk;
*/
// // Disable MPU
// HAL_MPU_Disable(); // Bootloader (0x08020000 - 0x0803FFFF, 128 KiB, read-only)
MPU->RNR = MPU_REGION_NUMBER0;
// // Note: later entries overwrite previous ones MPU->RBAR = FLASH_BASE + 0x20000;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// /* LL_MPU_REGION_SIZE_128KB | LL_MPU_REGION_PRIV_RO_URO;
// // Boardloader (0x08000000 - 0x0800FFFF, 64 KiB, read-only, execute
// never) MPU->RBAR = FLASH_BASE | MPU_REGION_NUMBER0; MPU->RASR = // Storage#1 (0x08010000 - 0x0801FFFF, 64 KiB, read-write, execute never)
// MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH | MPU->RNR = MPU_REGION_NUMBER1;
// LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_PRIV_RO_URO | MPU_RASR_XN_Msk; MPU->RBAR = FLASH_BASE + 0x10000;
// */ MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS |
// // Bootloader (0x08020000 - 0x0803FFFF, 128 KiB, read-only) MPU_RASR_XN_Msk;
// MPU->RNR = MPU_REGION_NUMBER0;
// MPU->RBAR = FLASH_BASE + 0x20000; #ifdef USE_OPTIGA
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH | // Translations + Storage#2 - secret (0x08104000 - 0x0811FFFF, 112 KiB,
// LL_MPU_REGION_SIZE_128KB | LL_MPU_REGION_PRIV_RO_URO; // read-write, execute never)
MPU->RNR = MPU_REGION_NUMBER2;
// // Storage#1 (0x08010000 - 0x0801FFFF, 64 KiB, read-write, execute never) MPU->RBAR = FLASH_BASE + 0x100000;
// MPU->RNR = MPU_REGION_NUMBER1; MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// MPU->RBAR = FLASH_BASE + 0x10000; LL_MPU_REGION_SIZE_128KB | LL_MPU_REGION_FULL_ACCESS |
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH | MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0x01);
// LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS | #else
// MPU_RASR_XN_Msk; // Translations + Storage#2 (0x08100000 - 0x0811FFFF, 128 KiB, read-write,
// // Storage#2 (0x08110000 - 0x0811FFFF, 64 KiB, read-write, execute never) // execute never)
// MPU->RNR = MPU_REGION_NUMBER2; MPU->RNR = MPU_REGION_NUMBER2;
// MPU->RBAR = FLASH_BASE + 0x110000; MPU->RBAR = FLASH_BASE + 0x100000;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH | MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS | LL_MPU_REGION_SIZE_128KB | LL_MPU_REGION_FULL_ACCESS |
// MPU_RASR_XN_Msk; MPU_RASR_XN_Msk;
#endif
// // Firmware (0x08040000 - 0x080FFFFF, 6 * 128 KiB = 1024 KiB except 2/8
// at // Firmware (0x08040000 - 0x080FFFFF, 6 * 128 KiB = 1024 KiB except 2/8 at
// // start = 768 KiB, read-only) // start = 768 KiB, read-only)
// MPU->RNR = MPU_REGION_NUMBER3; MPU->RNR = MPU_REGION_NUMBER3;
// MPU->RBAR = FLASH_BASE; MPU->RBAR = FLASH_BASE;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH | MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// LL_MPU_REGION_SIZE_1MB | LL_MPU_REGION_PRIV_RO_URO | LL_MPU_REGION_SIZE_1MB | LL_MPU_REGION_PRIV_RO_URO |
// MPU_SUBREGION_DISABLE(0x03); MPU_SUBREGION_DISABLE(0x03);
// // Firmware extra (0x08120000 - 0x081FFFFF, 7 * 128 KiB = 1024 KiB except // Firmware extra (0x08120000 - 0x081FFFFF, 7 * 128 KiB = 1024 KiB except 1/8
// 1/8 // at start = 896 KiB, read-only)
// // at start = 896 KiB, read-only) MPU->RNR = MPU_REGION_NUMBER4;
// MPU->RNR = MPU_REGION_NUMBER4; MPU->RBAR = FLASH_BASE + 0x100000;
// MPU->RBAR = FLASH_BASE + 0x100000; MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH | LL_MPU_REGION_SIZE_1MB | LL_MPU_REGION_PRIV_RO_URO |
// LL_MPU_REGION_SIZE_1MB | LL_MPU_REGION_PRIV_RO_URO | MPU_SUBREGION_DISABLE(0x01);
// MPU_SUBREGION_DISABLE(0x01);
// SRAM (0x20000000 - 0x2002FFFF, 192 KiB = 256 KiB except 2/8 at end,
// // SRAM (0x20000000 - 0x2002FFFF, 192 KiB = 256 KiB except 2/8 at end, // read-write, execute never)
// // read-write, execute never) MPU->RNR = MPU_REGION_NUMBER5;
// MPU->RNR = MPU_REGION_NUMBER5; MPU->RBAR = SRAM_BASE;
// MPU->RBAR = SRAM_BASE; MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM |
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM | LL_MPU_REGION_SIZE_256KB | LL_MPU_REGION_FULL_ACCESS |
// LL_MPU_REGION_SIZE_256KB | LL_MPU_REGION_FULL_ACCESS | MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0xC0);
// MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0xC0);
#ifdef USE_SDRAM
// #ifdef USE_SDRAM // Peripherals (0x40000000 - 0x5FFFFFFF, read-write, execute never)
// // Peripherals (0x40000000 - 0x5FFFFFFF, read-write, execute never) // SDRAM (0xC0000000 - 0xDFFFFFFF, read-write, execute never)
// // SDRAM (0xC0000000 - 0xDFFFFFFF, read-write, execute never) MPU->RNR = MPU_REGION_NUMBER6;
// MPU->RNR = MPU_REGION_NUMBER6; MPU->RBAR = 0;
// MPU->RBAR = 0; MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_PERIPH |
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_PERIPH | LL_MPU_REGION_SIZE_4GB | LL_MPU_REGION_FULL_ACCESS |
// LL_MPU_REGION_SIZE_4GB | LL_MPU_REGION_FULL_ACCESS | MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0xBB);
// MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0xBB); #else
// #else // Peripherals (0x40000000 - 0x5FFFFFFF, read-write, execute never)
// // Peripherals (0x40000000 - 0x5FFFFFFF, read-write, execute never) // External RAM (0x60000000 - 0x7FFFFFFF, read-write, execute never)
// // External RAM (0x60000000 - 0x7FFFFFFF, read-write, execute never) MPU->RNR = MPU_REGION_NUMBER6;
// MPU->RNR = MPU_REGION_NUMBER6; MPU->RBAR = PERIPH_BASE;
// MPU->RBAR = PERIPH_BASE; MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_PERIPH |
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_PERIPH | LL_MPU_REGION_SIZE_1GB | LL_MPU_REGION_FULL_ACCESS |
// LL_MPU_REGION_SIZE_1GB | LL_MPU_REGION_FULL_ACCESS | MPU_RASR_XN_Msk;
// MPU_RASR_XN_Msk; #endif
// #endif
#if defined STM32F427xx || defined STM32F429xx
// #if defined STM32F427xx || defined STM32F429xx // CCMRAM (0x10000000 - 0x1000FFFF, read-write, execute never)
// // CCMRAM (0x10000000 - 0x1000FFFF, read-write, execute never) MPU->RNR = MPU_REGION_NUMBER7;
// MPU->RNR = MPU_REGION_NUMBER7; MPU->RBAR = CCMDATARAM_BASE;
// MPU->RBAR = CCMDATARAM_BASE; MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM |
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM | LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS |
// LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS | MPU_RASR_XN_Msk;
// MPU_RASR_XN_Msk; #elif STM32F405xx
// #elif STM32F405xx // no CCMRAM
// // no CCMRAM #else
// #else #error Unsupported MCU
// #error Unsupported MCU #endif
// #endif
// Enable MPU
// // Enable MPU HAL_MPU_Enable(LL_MPU_CTRL_HARDFAULT_NMI);
// HAL_MPU_Enable(LL_MPU_CTRL_HARDFAULT_NMI);
__asm__ volatile("dsb");
// __asm__ volatile("dsb"); __asm__ volatile("isb");
// __asm__ volatile("isb");
} }
void mpu_config_prodtest(void) { void mpu_config_prodtest(void) {

Loading…
Cancel
Save