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feat(core): allow access to translations area in firmware

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tychovrahe/fw_translations/mpu
tychovrahe 6 months ago
parent f46e7e65cb
commit 0f3e082e06
1 changed files with 103 additions and 104 deletions
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core/embed/trezorhal/stm32f4/mpu.c
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@ -101,110 +101,109 @@ void mpu_config_bootloader(void) {
}
void mpu_config_firmware(void) {
// TODO: Michal said this should be commented, but even with return below
// the hardware is not working (blank screen on TT)
// It has these warnings during the FW build:
// - warning: _popcountsi2.o: missing .note.GNU-stack section implies
// executable stack
// - NOTE: This behaviour is deprecated and will be removed in a future
// version of the linker
// - warning: build/firmware/firmware.elf has a LOAD segment with RWX
// permissions
// return;
// // Disable MPU
// HAL_MPU_Disable();
// // Note: later entries overwrite previous ones
// /*
// // Boardloader (0x08000000 - 0x0800FFFF, 64 KiB, read-only, execute
// never) MPU->RBAR = FLASH_BASE | MPU_REGION_NUMBER0; MPU->RASR =
// MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_PRIV_RO_URO | MPU_RASR_XN_Msk;
// */
// // Bootloader (0x08020000 - 0x0803FFFF, 128 KiB, read-only)
// MPU->RNR = MPU_REGION_NUMBER0;
// MPU->RBAR = FLASH_BASE + 0x20000;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// LL_MPU_REGION_SIZE_128KB | LL_MPU_REGION_PRIV_RO_URO;
// // Storage#1 (0x08010000 - 0x0801FFFF, 64 KiB, read-write, execute never)
// MPU->RNR = MPU_REGION_NUMBER1;
// MPU->RBAR = FLASH_BASE + 0x10000;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS |
// MPU_RASR_XN_Msk;
// // Storage#2 (0x08110000 - 0x0811FFFF, 64 KiB, read-write, execute never)
// MPU->RNR = MPU_REGION_NUMBER2;
// MPU->RBAR = FLASH_BASE + 0x110000;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS |
// MPU_RASR_XN_Msk;
// // Firmware (0x08040000 - 0x080FFFFF, 6 * 128 KiB = 1024 KiB except 2/8
// at
// // start = 768 KiB, read-only)
// MPU->RNR = MPU_REGION_NUMBER3;
// MPU->RBAR = FLASH_BASE;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// LL_MPU_REGION_SIZE_1MB | LL_MPU_REGION_PRIV_RO_URO |
// MPU_SUBREGION_DISABLE(0x03);
// // Firmware extra (0x08120000 - 0x081FFFFF, 7 * 128 KiB = 1024 KiB except
// 1/8
// // at start = 896 KiB, read-only)
// MPU->RNR = MPU_REGION_NUMBER4;
// MPU->RBAR = FLASH_BASE + 0x100000;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
// LL_MPU_REGION_SIZE_1MB | LL_MPU_REGION_PRIV_RO_URO |
// MPU_SUBREGION_DISABLE(0x01);
// // SRAM (0x20000000 - 0x2002FFFF, 192 KiB = 256 KiB except 2/8 at end,
// // read-write, execute never)
// MPU->RNR = MPU_REGION_NUMBER5;
// MPU->RBAR = SRAM_BASE;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM |
// LL_MPU_REGION_SIZE_256KB | LL_MPU_REGION_FULL_ACCESS |
// MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0xC0);
// #ifdef USE_SDRAM
// // Peripherals (0x40000000 - 0x5FFFFFFF, read-write, execute never)
// // SDRAM (0xC0000000 - 0xDFFFFFFF, read-write, execute never)
// MPU->RNR = MPU_REGION_NUMBER6;
// MPU->RBAR = 0;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_PERIPH |
// LL_MPU_REGION_SIZE_4GB | LL_MPU_REGION_FULL_ACCESS |
// MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0xBB);
// #else
// // Peripherals (0x40000000 - 0x5FFFFFFF, read-write, execute never)
// // External RAM (0x60000000 - 0x7FFFFFFF, read-write, execute never)
// MPU->RNR = MPU_REGION_NUMBER6;
// MPU->RBAR = PERIPH_BASE;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_PERIPH |
// LL_MPU_REGION_SIZE_1GB | LL_MPU_REGION_FULL_ACCESS |
// MPU_RASR_XN_Msk;
// #endif
// #if defined STM32F427xx || defined STM32F429xx
// // CCMRAM (0x10000000 - 0x1000FFFF, read-write, execute never)
// MPU->RNR = MPU_REGION_NUMBER7;
// MPU->RBAR = CCMDATARAM_BASE;
// MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM |
// LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS |
// MPU_RASR_XN_Msk;
// #elif STM32F405xx
// // no CCMRAM
// #else
// #error Unsupported MCU
// #endif
// // Enable MPU
// HAL_MPU_Enable(LL_MPU_CTRL_HARDFAULT_NMI);
// __asm__ volatile("dsb");
// __asm__ volatile("isb");
// Disable MPU
HAL_MPU_Disable();
// Note: later entries overwrite previous ones
/*
// Boardloader (0x08000000 - 0x0800FFFF, 64 KiB, read-only, execute never)
MPU->RBAR = FLASH_BASE | MPU_REGION_NUMBER0;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_PRIV_RO_URO | MPU_RASR_XN_Msk;
*/
// Bootloader (0x08020000 - 0x0803FFFF, 128 KiB, read-only)
MPU->RNR = MPU_REGION_NUMBER0;
MPU->RBAR = FLASH_BASE + 0x20000;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
LL_MPU_REGION_SIZE_128KB | LL_MPU_REGION_PRIV_RO_URO;
// Storage#1 (0x08010000 - 0x0801FFFF, 64 KiB, read-write, execute never)
MPU->RNR = MPU_REGION_NUMBER1;
MPU->RBAR = FLASH_BASE + 0x10000;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS |
MPU_RASR_XN_Msk;
#ifdef USE_OPTIGA
// Translations + Storage#2 - secret (0x08104000 - 0x0811FFFF, 112 KiB,
// read-write, execute never)
MPU->RNR = MPU_REGION_NUMBER2;
MPU->RBAR = FLASH_BASE + 0x100000;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
LL_MPU_REGION_SIZE_128KB | LL_MPU_REGION_FULL_ACCESS |
MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0x01);
#else
// Translations + Storage#2 (0x08100000 - 0x0811FFFF, 128 KiB, read-write,
// execute never)
MPU->RNR = MPU_REGION_NUMBER2;
MPU->RBAR = FLASH_BASE + 0x100000;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
LL_MPU_REGION_SIZE_128KB | LL_MPU_REGION_FULL_ACCESS |
MPU_RASR_XN_Msk;
#endif
// Firmware (0x08040000 - 0x080FFFFF, 6 * 128 KiB = 1024 KiB except 2/8 at
// start = 768 KiB, read-only)
MPU->RNR = MPU_REGION_NUMBER3;
MPU->RBAR = FLASH_BASE;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
LL_MPU_REGION_SIZE_1MB | LL_MPU_REGION_PRIV_RO_URO |
MPU_SUBREGION_DISABLE(0x03);
// Firmware extra (0x08120000 - 0x081FFFFF, 7 * 128 KiB = 1024 KiB except 1/8
// at start = 896 KiB, read-only)
MPU->RNR = MPU_REGION_NUMBER4;
MPU->RBAR = FLASH_BASE + 0x100000;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_FLASH |
LL_MPU_REGION_SIZE_1MB | LL_MPU_REGION_PRIV_RO_URO |
MPU_SUBREGION_DISABLE(0x01);
// SRAM (0x20000000 - 0x2002FFFF, 192 KiB = 256 KiB except 2/8 at end,
// read-write, execute never)
MPU->RNR = MPU_REGION_NUMBER5;
MPU->RBAR = SRAM_BASE;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM |
LL_MPU_REGION_SIZE_256KB | LL_MPU_REGION_FULL_ACCESS |
MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0xC0);
#ifdef USE_SDRAM
// Peripherals (0x40000000 - 0x5FFFFFFF, read-write, execute never)
// SDRAM (0xC0000000 - 0xDFFFFFFF, read-write, execute never)
MPU->RNR = MPU_REGION_NUMBER6;
MPU->RBAR = 0;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_PERIPH |
LL_MPU_REGION_SIZE_4GB | LL_MPU_REGION_FULL_ACCESS |
MPU_RASR_XN_Msk | MPU_SUBREGION_DISABLE(0xBB);
#else
// Peripherals (0x40000000 - 0x5FFFFFFF, read-write, execute never)
// External RAM (0x60000000 - 0x7FFFFFFF, read-write, execute never)
MPU->RNR = MPU_REGION_NUMBER6;
MPU->RBAR = PERIPH_BASE;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_PERIPH |
LL_MPU_REGION_SIZE_1GB | LL_MPU_REGION_FULL_ACCESS |
MPU_RASR_XN_Msk;
#endif
#if defined STM32F427xx || defined STM32F429xx
// CCMRAM (0x10000000 - 0x1000FFFF, read-write, execute never)
MPU->RNR = MPU_REGION_NUMBER7;
MPU->RBAR = CCMDATARAM_BASE;
MPU->RASR = MPU_RASR_ENABLE_Msk | MPU_RASR_ATTR_SRAM |
LL_MPU_REGION_SIZE_64KB | LL_MPU_REGION_FULL_ACCESS |
MPU_RASR_XN_Msk;
#elif STM32F405xx
// no CCMRAM
#else
#error Unsupported MCU
#endif
// Enable MPU
HAL_MPU_Enable(LL_MPU_CTRL_HARDFAULT_NMI);
__asm__ volatile("dsb");
__asm__ volatile("isb");
}
void mpu_config_prodtest(void) {

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