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chore(core): remove residual optiga_hal symlink

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tychovrahe 2024-11-20 10:58:52 +01:00 committed by TychoVrahe
parent a7f6930c78
commit 007a9a4f3b
6 changed files with 4 additions and 5 deletions
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0
core/embed/sec/optiga/stm32f4/optiga_hal.c → core/embed/sec/optiga/stm32/optiga_hal.c
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1
core/embed/sec/optiga/stm32u5/optiga_hal.c
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@ -1 +0,0 @@
../stm32f4/optiga_hal.c

2
core/site_scons/models/T2B1/trezor_r_v10.py
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@ -78,7 +78,7 @@ def configure(
if "optiga" in features_wanted:
sources += ["embed/io/i2c_bus/stm32f4/i2c_bus.c"]
sources += ["embed/sec/optiga/stm32f4/optiga_hal.c"]
sources += ["embed/sec/optiga/stm32/optiga_hal.c"]
sources += ["embed/sec/optiga/optiga.c"]
sources += ["embed/sec/optiga/optiga_commands.c"]
sources += ["embed/sec/optiga/optiga_transport.c"]

2
core/site_scons/models/T3B1/trezor_t3b1_revB.py
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@ -70,7 +70,7 @@ def configure(
if "optiga" in features_wanted:
sources += ["embed/io/i2c_bus/stm32u5/i2c_bus.c"]
sources += ["embed/sec/optiga/stm32u5/optiga_hal.c"]
sources += ["embed/sec/optiga/stm32/optiga_hal.c"]
sources += ["embed/sec/optiga/optiga.c"]
sources += ["embed/sec/optiga/optiga_commands.c"]
sources += ["embed/sec/optiga/optiga_transport.c"]

2
core/site_scons/models/T3T1/trezor_t3t1_revE.py
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@ -110,7 +110,7 @@ def configure(
features_available.append("dma2d")
if "optiga" in features_wanted:
sources += ["embed/sec/optiga/stm32u5/optiga_hal.c"]
sources += ["embed/sec/optiga/stm32/optiga_hal.c"]
sources += ["embed/sec/optiga/optiga.c"]
sources += ["embed/sec/optiga/optiga_commands.c"]
sources += ["embed/sec/optiga/optiga_transport.c"]

2
core/site_scons/models/T3W1/trezor_t3w1_revA.py
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@ -84,7 +84,7 @@ def configure(
]
if "optiga" in features_wanted:
sources += ["embed/sec/optiga/stm32u5/optiga_hal.c"]
sources += ["embed/sec/optiga/stm32/optiga_hal.c"]
sources += ["embed/sec/optiga/optiga.c"]
sources += ["embed/sec/optiga/optiga_commands.c"]
sources += ["embed/sec/optiga/optiga_transport.c"]