mirror of
https://github.com/bitdefender/bddisasm.git
synced 2024-12-01 11:58:19 +00:00
752bc626c4
Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests. |
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| .. | ||
| cpuid.dat | ||
| flags.dat | ||
| modes.dat | ||
| prefixes.dat | ||
| table_0F_3A.dat | ||
| table_0F_38.dat | ||
| table_0F.dat | ||
| table_3dnow.dat | ||
| table_base.dat | ||
| table_evex1.dat | ||
| table_evex2.dat | ||
| table_evex3.dat | ||
| table_fpu.dat | ||
| table_vex1.dat | ||
| table_vex2.dat | ||
| table_vex3.dat | ||
| table_xop.dat | ||