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08096172cc
bddisasm/bddisasm_test/special
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Andrei Vlad LUTAS 08096172cc Multiple improvements 
- New shemu flag - SHEMU_FLAG_SIDT, set when sheu encounters a SIDT in ring0.
- Added the CET Tracked flag to SYSCLAL, SYSENTER and INT n instructions.
- Fixed Do Not Track prefix recognition for CALL and JMP in long-mode.
- Fixed MONITOR and MONITORX implicit operands - the rAX register encodes a virtual address that will be used as the monitored range. That address is subject to a 1 byte load.
- Fixed RMPADJUST and RMPUPDATE implicit operands - the rAX register encodes a virtual address, and the rCX register encodes a virtual address of the RMP updated entry.
2021-08-31 13:37:50 +03:00
..
amx_64 Initial commit. 2020-07-21 11:19:18 +03:00
amx_64_skip Multiple changes 2021-07-08 12:40:39 +03:00
amx_64_skip.asm Multiple changes 2021-07-08 12:40:39 +03:00
amx_64_skip.result Multiple changes 2021-07-08 12:40:39 +03:00
amx_64.asm Initial commit. 2020-07-21 11:19:18 +03:00
amx_64.result Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. 2021-05-17 09:04:34 +03:00
avx2gather_1_64 Initial commit. 2020-07-21 11:19:18 +03:00
avx2gather_1_64_skip Multiple changes 2021-07-08 12:40:39 +03:00
avx2gather_1_64_skip.asm Multiple changes 2021-07-08 12:40:39 +03:00
avx2gather_1_64_skip.result Multiple changes 2021-07-08 12:40:39 +03:00
avx2gather_1_64.asm Initial commit. 2020-07-21 11:19:18 +03:00
avx2gather_1_64.result Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. 2021-05-17 09:04:34 +03:00
avx2gather_2_64 Initial commit. 2020-07-21 11:19:18 +03:00
avx2gather_2_64_skip Multiple changes 2021-07-08 12:40:39 +03:00
avx2gather_2_64_skip.asm Multiple changes 2021-07-08 12:40:39 +03:00
avx2gather_2_64_skip.result Multiple changes 2021-07-08 12:40:39 +03:00
avx2gather_2_64.asm Initial commit. 2020-07-21 11:19:18 +03:00
avx2gather_2_64.result Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. 2021-05-17 09:04:34 +03:00
avx2gather_3_64 Initial commit. 2020-07-21 11:19:18 +03:00
avx2gather_3_64_skip Multiple changes 2021-07-08 12:40:39 +03:00
avx2gather_3_64_skip.asm Multiple changes 2021-07-08 12:40:39 +03:00
avx2gather_3_64_skip.result Multiple changes 2021-07-08 12:40:39 +03:00
avx2gather_3_64.asm Initial commit. 2020-07-21 11:19:18 +03:00
avx2gather_3_64.result Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. 2021-05-17 09:04:34 +03:00
cr8_32 Initial commit. 2020-07-21 11:19:18 +03:00
cr8_32.asm Initial commit. 2020-07-21 11:19:18 +03:00
cr8_32.result Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf. 2020-09-10 11:06:20 +03:00
ignorew_evex_32 Multiple changes 2021-07-08 12:40:39 +03:00
ignorew_evex_32.result Multiple changes 2021-07-08 12:40:39 +03:00
ignorew_evex_64 Multiple changes 2021-07-08 12:40:39 +03:00
ignorew_evex_64.result Multiple changes 2021-07-08 12:40:39 +03:00
invalid_32 Initial commit. 2020-07-21 11:19:18 +03:00
invalid_32_skip Multiple changes 2021-07-08 12:40:39 +03:00
invalid_32_skip.asm Multiple changes 2021-07-08 12:40:39 +03:00
invalid_32_skip.result Multiple improvements 2021-08-31 13:37:50 +03:00
invalid_32.asm Initial commit. 2020-07-21 11:19:18 +03:00
invalid_32.result Fixed some static code check warnings. 2020-09-21 12:16:45 +03:00
invalid_64 Initial commit. 2020-07-21 11:19:18 +03:00
invalid_64_skip Multiple changes 2021-07-08 12:40:39 +03:00
invalid_64_skip.asm Multiple changes 2021-07-08 12:40:39 +03:00
invalid_64_skip.result Multiple changes 2021-07-08 12:40:39 +03:00
invalid_64.asm Initial commit. 2020-07-21 11:19:18 +03:00
invalid_64.result Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf. 2020-09-10 11:06:20 +03:00
invalid_evex_64_skip Multiple changes 2021-07-08 12:40:39 +03:00
invalid_evex_64_skip.asm Multiple changes 2021-07-08 12:40:39 +03:00
invalid_evex_64_skip.result Multiple changes 2021-07-08 12:40:39 +03:00
long_64 Initial commit. 2020-07-21 11:19:18 +03:00
long_64.asm Initial commit. 2020-07-21 11:19:18 +03:00
long_64.result Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf. 2020-09-10 11:06:20 +03:00
movcrdr_64 Initial commit. 2020-07-21 11:19:18 +03:00
movcrdr_64.asm Initial commit. 2020-07-21 11:19:18 +03:00
movcrdr_64.result Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf. 2020-09-10 11:06:20 +03:00
only_32 Initial commit. 2020-07-21 11:19:18 +03:00
only_32.asm Initial commit. 2020-07-21 11:19:18 +03:00
only_32.result Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf. 2020-09-10 11:06:20 +03:00
only_64 Initial commit. 2020-07-21 11:19:18 +03:00
only_64.asm Initial commit. 2020-07-21 11:19:18 +03:00
only_64.result Multiple improvements 2021-08-31 13:37:50 +03:00
regressions_32 Fixed RET with immediate - the immediate is not sign-extended. 2020-07-23 14:08:01 +03:00
regressions_32.asm Fixed RET with immediate - the immediate is not sign-extended. 2020-07-23 14:08:01 +03:00
regressions_32.result Multiple improvements 2021-08-31 13:37:50 +03:00
regressions_64 Fixed RET with immediate - the immediate is not sign-extended. 2020-07-23 14:08:01 +03:00
regressions_64.asm Fixed RET with immediate - the immediate is not sign-extended. 2020-07-23 14:08:01 +03:00
regressions_64.result Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. 2021-05-17 09:04:34 +03:00