38592edf31Removed old test files.
Andrei Vlad LUTAS
2021-08-31 13:49:29 +0300
08096172ccMultiple improvements - New shemu flag - SHEMU_FLAG_SIDT, set when sheu encounters a SIDT in ring0. - Added the CET Tracked flag to SYSCLAL, SYSENTER and INT n instructions. - Fixed Do Not Track prefix recognition for CALL and JMP in long-mode. - Fixed MONITOR and MONITORX implicit operands - the rAX register encodes a virtual address that will be used as the monitored range. That address is subject to a 1 byte load. - Fixed RMPADJUST and RMPUPDATE implicit operands - the rAX register encodes a virtual address, and the rCX register encodes a virtual address of the RMP updated entry.
v1.34.4
Andrei Vlad LUTAS
2021-08-31 13:37:50 +0300
5a617986b7Added new shemu flag: SHEMU_FLAG_SUD_ACCESS is raised whenever the code accesses the SharedUserData page.
v1.34.2
Andrei Vlad LUTAS
2021-08-16 12:34:41 +0300
c8735b437aFixed NEG emulation - make sure flags are set.
Andrei Vlad LUTAS
2021-08-10 14:46:39 +0300
f6050661d5Multiple improvements in bdshemu Fixed an emulation bug for MOVZX and MOVSX instructions (https://github.com/bitdefender/bddisasm/issues/48) New shellcode flag - call tot Wow32 reserved. New shellcode flag - heaven's gate. New shellcode flag - stack-pivot. Moved bdshemu tests in a password protected zip file, so it doesn't trigger AV detections.
Andrei Vlad LUTAS
2021-08-10 11:43:51 +0300
c3a6ea1c25Updated SEAMCALL specs according to Intel® Trust Domain CPU Architectural Extensions 343754-002US May 2021.
Andrei Vlad LUTAS
2021-05-31 13:34:52 +0300
d053de409fAlthough not stated in the SDM, VMCALL, VMLAUNCH, VMRESUME and VMXOFF refuse any prefix (66, F3, F2).
Andrei Vlad LUTAS
2021-05-31 10:42:26 +0300
072f6e059bBuild improvements Exclude string constants from build if BDDISASM_NO_FORMAT is defined. Use extern "C" when declaring the public bddisasm/bdshemu functions. Include wmmintrin.h for AES intrinisics when building using LLVM/clang.
Andrei Vlad LUTAS
2021-05-17 09:52:04 +0300
10dc00681dUpdated version for pybddisasm build.
Andrei Vlad LUTAS
2021-05-17 09:13:27 +0300
f7bf814bbcFlag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. Bypass self-writes option in bdshemu - if set, bdshemu will not proceed to commit modifications made by the shellcode to itself.
Andrei Vlad LUTAS
2021-05-17 09:04:34 +0300
283c00b4c7cmake: Format the cmake scripts
Ionel-Cristinel ANICHITEI
2021-03-30 12:20:47 +0300
3495a7cc84cmake: Various improvements, especially to the way the bddisasm package is consumed
Ionel-Cristinel ANICHITEI
2021-03-30 12:20:31 +0300
fccf11915dAdded support for Intel FRED and LKGS instructions.
Andrei Vlad LUTAS
2021-03-15 14:05:44 +0200
f7be5a7bbdIncremented version.
v1.31.8
Andrei Vlad LUTAS
2021-02-23 18:17:21 +0200
15e5e2db63Fixed several RFLAGS setting issues with airthmetic and shift instructions.
Andrei Vlad LUTAS
2021-02-23 18:11:40 +0200
37d47ef7e7Display instruction bitfields support. Using the `-bits` option, the various bits inside the EVEX, VEX, XOP, ModR/M and SIB can be displayed.
v1.31.7
Andrei Vlad LUTAS
2021-02-19 11:10:41 +0200
057d326433Specify -maes when building bdshemu
Ionel-Cristinel ANICHITEI
2020-12-04 11:45:10 +0200
e552aef1f5Add march=westmere in bdshemu Makefile as well.
Andrei Vlad LUTAS
2020-12-04 11:16:21 +0200
e0c6f9e374Specify westmere arch on pybddisasm build.
Andrei Vlad LUTAS
2020-12-04 11:05:49 +0200
f8a3011a49Added support for AESDEC, AESDECLAST and AESIMC emulation, using compiler intrinsics - they will be used only if the SHEMU_OPT_SUPPORT_AES is set (so the integrator can properly check for AES-NI support in hardware). Fixed shemu option on Linux - make sure proper RIP is provided.
Andrei Vlad LUTAS
2020-12-04 10:52:56 +0200
ci: Update microsoft/setup-msbuild to v1.0.2
Anichitei Ionel-Cristinel
2020-11-17 10:41:59 +0200
e89f56289dAs per Intel SDM version 73 released in November 2020, make sure we don't decode 32-bit EVEX instructions that have EVEX.V' cleared, and 64-bit EVEX instructions that don't use EVEX.V' field, but have it cleared.
Andrei Vlad LUTAS
2020-11-17 10:36:26 +0200
67da1892d4Fetch the instruction bytes inside the Instrux when first entering NdDecode, and then use that buffer for further decoding.
Andrei Vlad LUTAS
2020-11-12 10:57:16 +0200
460e544652Fixed build.
Andrei Vlad LUTAS
2020-11-09 09:52:49 +0200
2b2dbe2aeaD64 flag for ENTER instruction.
Andrei Vlad LUTAS
2020-11-07 12:12:28 +0200
e26971b4f0Added missing Default 64 flag for the ENTER instruction. On AMD, operand size is never forced to 64 bit - instead, it only defaults to 64 bit, which means that 0x66 can be used to encode 16 bit version of the instructions.
Andrei Vlad LUTAS
2020-11-06 14:19:22 +0200
7a0fa449bcDisassemble 4X90 as NOP as long as Rex.B is 0. Disassemble as XCHG only if Rex.B bit is set (promoting the use of R8 register).
v1.31.0
Andrei Vlad LUTAS
2020-10-09 14:55:39 +0300
9652450125Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
Andrei Vlad LUTAS
2020-10-05 13:19:03 +0300