Commit Graph

4 Commits (f7bf814bbca47cf0d26a03be28b10cd3083628ce)

Author SHA1 Message Date
Andrei Vlad LUTAS f7bf814bbc Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write.
3 years ago
Andrei Vlad LUTAS 33078e4670 Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
4 years ago
Andrei Vlad LUTAS 4b2f2aee66 Added dedicated Prefetch operand access type.
4 years ago
Andrei Vlad LUTAS 752bc626c4 Fixed RET with immediate - the immediate is not sign-extended.
4 years ago