Anichitei Ionel-Cristinel
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802f2854cd
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Try Artifact Attestations
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2024-05-08 08:03:20 +03:00 |
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Andrei Vlad LUTAS
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1fa6505b28
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Build fix for macos.
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2024-05-07 17:48:44 +03:00 |
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Andrei Vlad LUTAS
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173e2e295d
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Do not use cpuid outside x86 architectures in disasmtool.
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2024-05-07 17:38:01 +03:00 |
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Andrei Vlad LUTAS
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9a66dc05c7
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Further fixed macos build.
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2024-05-07 17:27:44 +03:00 |
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Andrei Vlad LUTAS
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473eb0af62
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Fixed macos build.
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2024-05-07 17:22:33 +03:00 |
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Andrei Vlad LUTAS
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05d5632dea
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https://github.com/bitdefender/bddisasm/issues/89 - fixed comment.
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2024-05-07 17:03:07 +03:00 |
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Andrei Vlad LUTAS
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f32c0373ac
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Incremented revision to 2.1.4.
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2024-03-27 09:30:24 +02:00 |
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Andrei Vlad LUTAS
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44dc7c6cbb
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Updated changelog & Python binding version.
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2024-03-27 09:21:00 +02:00 |
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Andrei Vlad LUTAS
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4bc4636765
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https://github.com/bitdefender/bddisasm/issues/88 - removed (no longer needed) assert.
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2024-03-27 09:15:51 +02:00 |
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Andrei Vlad LUTAS
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37a8c94bc7
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Applied some of the syntax recomandations from https://cdrdv2.intel.com/v1/dl/getContent/817241.
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2024-03-04 12:48:18 +02:00 |
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Andrei Vlad LUTAS
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02cbe6a298
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https://github.com/bitdefender/bddisasm/issues/87 - added missing R access for the rIP operand for SYSCALL instructions; added missing SCS, rCX and rDX operands for SYSEXIT instruction.
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2024-02-27 09:45:05 +02:00 |
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Andrei Vlad LUTAS
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f6f93c4112
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Fixed pybddisasm version.
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2024-02-26 21:03:14 +02:00 |
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Andrei Vlad LUTAS
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3df189f093
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https://github.com/bitdefender/bddisasm/issues/87 - Fixed CALL instruction access for rIP operand - it must include read access, as the instruction pointer is saved on the stack.
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2024-02-26 20:53:42 +02:00 |
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vlutas
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2b12d0ab4b
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Merge pull request #86 from oberrich/patch-1
Fix typo in bdshemu.c
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2024-02-26 10:52:33 +02:00 |
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oberrich
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f7410a083a
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Fix typo in bdshemu.c
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2024-02-26 05:13:24 +01:00 |
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vlutas
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8f95a2828d
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Merge pull request #85 from ianichitei/master
Various build improvements
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2024-02-23 15:44:04 +02:00 |
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Anichitei Ionel-Cristinel
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aeeafc414a
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build: Fix ci.yml
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2024-02-23 12:22:18 +02:00 |
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Anichitei Ionel-Cristinel
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afc3e94801
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build: Try to build on macos
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2024-02-23 12:21:11 +02:00 |
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Anichitei Ionel-Cristinel
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357b95d652
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build: Remove rapidjson dependency
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2024-02-23 12:16:08 +02:00 |
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Anichitei Ionel-Cristinel
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3beab3a3ee
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build: Use -march=native
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2024-02-23 11:44:03 +02:00 |
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Andrei Vlad LUTAS
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40d53c6433
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Removed unused declaration.
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2024-02-22 15:03:19 +02:00 |
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Anichitei Ionel-Cristinel
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00a9640b73
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rsbddisasm: Update bddisasm-sys dependency version
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2024-02-21 08:04:25 +02:00 |
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Anichitei Ionel-Cristinel
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abc9657c78
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rsbddisasm: Bump version in install instructions
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2024-02-21 08:02:20 +02:00 |
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Anichitei Ionel-Cristinel
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b5ac0a30b9
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Update Cargo.toml
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2024-02-21 08:00:40 +02:00 |
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Anichitei Ionel-Cristinel
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ba14104087
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rsbddisasm: Update bindgen to 0.62.0
See https://github.com/rust-lang/rust-bindgen/issues/2312
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2024-02-20 14:46:59 +02:00 |
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Andrei KISARI
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698686ab14
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Update headers for pybddisasm.
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2024-02-20 14:35:21 +02:00 |
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Anichitei Ionel-Cristinel
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fbe5c1375d
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Update ci.yml
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2024-02-20 14:06:32 +02:00 |
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Anichitei Ionel-Cristinel
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570fa2bb62
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ci: Suppress cppcheck objectIndex warning
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2024-02-20 14:05:45 +02:00 |
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Andrei Vlad LUTAS
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fad9c7e35c
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BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
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2024-02-20 13:39:22 +02:00 |
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Ionel-Cristinel ANICHITEI
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727c87ecc4
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rsbddisasm: Update bindings
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2023-07-21 10:14:31 +03:00 |
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Andrei Vlad LUTAS
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f53cbc51e2
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Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
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2023-07-21 09:38:49 +03:00 |
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Ionel-Cristinel ANICHITEI
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be0969824c
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rsbddisasm: Update CHANGELOG
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2023-07-01 10:50:49 +03:00 |
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Ionel-Cristinel ANICHITEI
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fbb38f1518
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#82: Handle 0 in OpSize::from_raw
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2023-07-01 10:44:37 +03:00 |
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Anichitei Ionel-Cristinel
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935e2dfe5b
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Merge pull request #81 from bitdefender/ci-updates
CI actions updates
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2023-06-27 14:57:15 +03:00 |
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Anichitei Ionel-Cristinel
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b90ed49d33
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ci: Update setup-msbuild to 1.3
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2023-06-27 14:52:22 +03:00 |
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Anichitei Ionel-Cristinel
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b71ad7e6d9
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ci: Update upload-release-assets to v2.0.2
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2023-06-27 14:45:14 +03:00 |
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Anichitei Ionel-Cristinel
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aa362fa43e
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ci: Update checkout to v3
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2023-06-27 14:32:31 +03:00 |
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Andrei KISARI
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11e6a3e208
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Merge pull request #80 from akisari/master
Use SWIG to create bindings between C and Python.
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2023-06-26 11:42:01 +03:00 |
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Andrei KISARI
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1384893052
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Update copyright.
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2023-06-26 10:40:30 +03:00 |
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Andrei KISARI
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455286ca13
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Fix build.
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2023-06-22 15:14:05 +03:00 |
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Andrei KISARI
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4f182b2c11
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Use SWIG to create bindings between C and Python.
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2023-06-22 14:54:41 +03:00 |
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BITDEFENDER\vlutas
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096b583c25
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Tiny comment fix.
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2023-06-02 11:22:52 +03:00 |
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BITDEFENDER\vlutas
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f293c936ee
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Optimized ror/rol/rcr/rcl instruction emulation - don't use slow loops anymore.
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2023-06-01 21:28:30 +03:00 |
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Ionel-Cristinel ANICHITEI
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d16f1d8ba3
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bdshemu_fuzz: Update build scripts
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2023-04-05 11:06:10 +03:00 |
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Ionel-Cristinel ANICHITEI
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3beaac8ae2
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Update bindings
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2023-04-05 10:02:41 +03:00 |
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BITDEFENDER\vlutas
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124521beb5
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Added support for Intel AMX-COMPLEX instructions.
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2023-04-05 09:45:07 +03:00 |
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BITDEFENDER\vlutas
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ee6cdd6cb6
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Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
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2023-02-09 10:54:45 +02:00 |
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BITDEFENDER\vlutas
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24665b0531
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Switched from nil to n/a naming for absent operands, as it is more obvious.
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2023-02-08 17:44:45 +02:00 |
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BITDEFENDER\vlutas
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fc6059109d
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Improved comments & improved vector length specifiers.
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2023-02-04 12:02:05 +02:00 |
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BITDEFENDER\vlutas
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0093439855
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Added some comments.
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2023-02-02 22:10:56 +02:00 |
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