Andrei Vlad LUTAS
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767bf2e5c0
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Added support for new Intel AVX 10.2 instructions.
Added support for AMD RMPREAD instruction.
Improved EVEX decoding, including the new U bit.
Fixed ENTER & LEAVE operands.
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2024-09-16 12:23:54 +03:00 |
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Andrei Vlad LUTAS
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91f04ed43b
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Fixed potential unaligned load, as reported by UBSAN.
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2024-05-28 19:20:38 +03:00 |
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Andrei Vlad LUTAS
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f32c0373ac
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Incremented revision to 2.1.4.
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2024-03-27 09:30:24 +02:00 |
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Andrei Vlad LUTAS
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37a8c94bc7
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Applied some of the syntax recomandations from https://cdrdv2.intel.com/v1/dl/getContent/817241.
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2024-03-04 12:48:18 +02:00 |
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Andrei Vlad LUTAS
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02cbe6a298
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https://github.com/bitdefender/bddisasm/issues/87 - added missing R access for the rIP operand for SYSCALL instructions; added missing SCS, rCX and rDX operands for SYSEXIT instruction.
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2024-02-27 09:45:05 +02:00 |
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Andrei Vlad LUTAS
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3df189f093
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https://github.com/bitdefender/bddisasm/issues/87 - Fixed CALL instruction access for rIP operand - it must include read access, as the instruction pointer is saved on the stack.
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2024-02-26 20:53:42 +02:00 |
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Andrei Vlad LUTAS
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fad9c7e35c
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BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
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2024-02-20 13:39:22 +02:00 |
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