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360 Commits 3 Branches 16 Tags 8.6 MiB
c282f06215
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8 Commits

Author SHA1 Message Date
vlutas
c282f06215
Add support for SIMD Exceptions reporting and new x86 ISAs (#108) 
* Add support for SIMD exceptions reporting in INSTRUX.
* Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4.

Co-authored-by: ianichitei (Rust bindings)
 2024-11-07 12:15:29 +02:00
Andrei Vlad LUTAS
767bf2e5c0 Added support for new Intel AVX 10.2 instructions. 
Added support for AMD RMPREAD instruction.
Improved EVEX decoding, including the new U bit.
Fixed ENTER & LEAVE operands.
 2024-09-16 12:23:54 +03:00
Andrei Vlad LUTAS
91f04ed43b Fixed potential unaligned load, as reported by UBSAN. 2024-05-28 19:20:38 +03:00
Andrei Vlad LUTAS
f32c0373ac Incremented revision to 2.1.4. 2024-03-27 09:30:24 +02:00
Andrei Vlad LUTAS
37a8c94bc7 Applied some of the syntax recomandations from https://cdrdv2.intel.com/v1/dl/getContent/817241. 2024-03-04 12:48:18 +02:00
Andrei Vlad LUTAS
02cbe6a298 https://github.com/bitdefender/bddisasm/issues/87 - added missing R access for the rIP operand for SYSCALL instructions; added missing SCS, rCX and rDX operands for SYSEXIT instruction. 2024-02-27 09:45:05 +02:00
Andrei Vlad LUTAS
3df189f093 https://github.com/bitdefender/bddisasm/issues/87 - Fixed CALL instruction access for rIP operand - it must include read access, as the instruction pointer is saved on the stack. 2024-02-26 20:53:42 +02:00
Andrei Vlad LUTAS
fad9c7e35c BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications. 2024-02-20 13:39:22 +02:00