BITDEFENDER\vlutas
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6dda2c122c
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Make sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied
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2 years ago |
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BITDEFENDER\vlutas
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1805a9edec
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Fixed flag setting for ADC, SBB, SAR and IMUL instructions.
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2 years ago |
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BITDEFENDER\vlutas
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fe6a937f51
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Switched to internally defined types.
WRUSSD and WRUSSQ cannot be executed when CPL != 0.
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2 years ago |
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BITDEFENDER\vlutas
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63e3ee22a9
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Fixed High8 handling in NdGetFullAccessMap.
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2 years ago |
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BITDEFENDER\vlutas
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2f50ce9b4e
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Improved REG_ID macros - make sure we include block addressing and High8 designator in the reg ID. Alsom, make sure the register size fits in, since the new tile register can be 1K in size, which previously overflowed...
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2 years ago |
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BITDEFENDER\vlutas
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7572adaeba
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Fixed INSTRUX size in setup.py.
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3 years ago |
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BITDEFENDER\vlutas
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433e723e07
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Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup.
Moved helper functions in bdhelpers.c.
Added a dedicated BranchInfo field inside INSTRUX, containing the most relevant branch information.
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3 years ago |
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Ionel-Cristinel ANICHITEI
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af3d23e3ff
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Move pybddisasm to the bindings directory
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3 years ago |
