6 Commits

Author	SHA1	Message	Date
Andrei Vlad LUTAS	42b6eceae6	* Add support for SIMD exceptions reporting in INSTRUX. ... * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)	2024-11-07 11:58:23 +02:00
Andrei Vlad LUTAS	10f06b9263	Updated CHANGELOG for v2.2.0.	2024-09-16 13:19:27 +03:00
Andrei Vlad LUTAS	91f04ed43b	Fixed potential unaligned load, as reported by UBSAN.	2024-05-28 19:20:38 +03:00
Andrei Vlad LUTAS	44dc7c6cbb	Updated changelog & Python binding version.	2024-03-27 09:21:00 +02:00
Andrei Vlad LUTAS	37a8c94bc7	Applied some of the syntax recomandations from https://cdrdv2.intel.com/v1/dl/getContent/817241.	2024-03-04 12:48:18 +02:00
Andrei Vlad LUTAS	fad9c7e35c	BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.	2024-02-20 13:39:22 +02:00