arno/bddisasm
1
0
Fork 0
mirror of https://github.com/bitdefender/bddisasm.git synced 2024-11-29 19:08:06 +00:00
Code Issues Releases Wiki Activity
f0804645f3
bddisasm/isagenerator/instructions/table_vex1.dat

307 lines
35 KiB
Plaintext
Raw Normal View History

Typo fixes in the instruction tables. Added a reference to the git repo in the documentation.
2020-07-21 13:38:09 +00:00
# Mnemonic Explicit Operands Implicit Operands Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops
Initial commit.
2020-07-21 08:19:18 +00:00
#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# 0x00 - 0x0F
# 0x10 - 0x1F
VMOVUPS Vx,Wx nil [vex m:1 p:0 l:x w:i 0x10 /r] s:AVX, t:DATAXFER, w:W|R, e:4
VMOVUPD Vx,Wx nil [vex m:1 p:1 l:x w:i 0x10 /r] s:AVX, t:DATAXFER, w:W|R, e:4
VMOVSS Vdq,Hdq,Uss nil [vex m:1 p:2 l:i w:i 0x10 /r:reg] s:AVX, t:DATAXFER, w:W|R|R, e:5
VMOVSS Vdq,Md nil [vex m:1 p:2 l:i w:i 0x10 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVSD Vdq,Hdq,Usd nil [vex m:1 p:3 l:i w:i 0x10 /r:reg] s:AVX, t:DATAXFER, w:W|R|R, e:5
VMOVSD Vdq,Mq nil [vex m:1 p:3 l:i w:i 0x10 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVUPS Wx,Vx nil [vex m:1 p:0 l:x w:i 0x11 /r] s:AVX, t:DATAXFER, w:W|R, e:4
VMOVUPD Wx,Vx nil [vex m:1 p:1 l:x w:i 0x11 /r] s:AVX, t:DATAXFER, w:W|R, e:4
VMOVSS Uss,Hss,Vss nil [vex m:1 p:2 l:i w:i 0x11 /r:reg] s:AVX, t:DATAXFER, w:W|R|R, e:5
VMOVSS Md,Vss nil [vex m:1 p:2 l:i w:i 0x11 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVSD Usd,Hsd,Vsd nil [vex m:1 p:3 l:i w:i 0x11 /r:reg] s:AVX, t:DATAXFER, w:W|R|R, e:5
VMOVSD Mq,Vsd nil [vex m:1 p:3 l:i w:i 0x11 /r:mem] s:AVX, t:DATAXFER, w:W|R|R, e:5
VMOVLPS Vdq,Hdq,Mq nil [vex m:1 p:0 l:0 w:i 0x12 /r:mem] s:AVX, t:DATAXFER, w:W|R|R, e:5
VMOVHLPS Vdq,Hdq,Udq nil [vex m:1 p:0 l:0 w:i 0x12 /r:reg] s:AVX, t:AVX, w:W|R|R, e:7
VMOVLPD Vdq,Hdq,Mq nil [vex m:1 p:1 l:0 w:i 0x12 /r:mem] s:AVX, t:DATAXFER, w:W|R|R, e:5
VMOVSLDUP Vx,Wx nil [vex m:1 p:2 l:x w:i 0x12 /r] s:AVX, t:AVX, w:W|R, e:4
VMOVDDUP Vdq,Wq nil [vex m:1 p:3 l:0 w:i 0x12 /r] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVDDUP Vqq,Wqq nil [vex m:1 p:3 l:1 w:i 0x12 /r] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVLPS Mq,Vdq nil [vex m:1 p:0 l:0 w:i 0x13 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVLPD Mq,Vdq nil [vex m:1 p:1 l:0 w:i 0x13 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5
VUNPCKLPS Vx,Hx,Wx nil [vex m:1 p:0 l:x w:i 0x14 /r] s:AVX, t:AVX, w:W|R|R, e:4
VUNPCKLPD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x14 /r] s:AVX, t:AVX, w:W|R|R, e:4
VUNPCKHPS Vx,Hx,Wx nil [vex m:1 p:0 l:x w:i 0x15 /r] s:AVX, t:AVX, w:W|R|R, e:4
VUNPCKHPD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x15 /r] s:AVX, t:AVX, w:W|R|R, e:4
VMOVHPS Vdq,Hdq,Mq nil [vex m:1 p:0 l:0 w:i 0x16 /r:mem] s:AVX, t:DATAXFER, w:W|R|R, e:5
VMOVLHPS Vdq,Hdq,Udq nil [vex m:1 p:0 l:0 w:i 0x16 /r:reg] s:AVX, t:AVX, w:W|R|R, e:7
VMOVHPD Vdq,Hdq,Mq nil [vex m:1 p:1 l:0 w:i 0x16 /r:mem] s:AVX, t:DATAXFER, w:W|R|R, e:5
VMOVSHDUP Vx,Wx nil [vex m:1 p:2 l:x w:i 0x16 /r] s:AVX, t:AVX, w:W|R, e:4
VMOVHPS Mq,Vdq nil [vex m:1 p:0 l:0 w:i 0x17 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVHPD Mq,Vdq nil [vex m:1 p:1 l:0 w:i 0x17 /r:mem] s:AVX, t:DATAXFER, w:W|R, e:5
# 0x20 - 0x2F
VMOVAPS Vx,Wx nil [vex m:1 p:0 l:x w:i 0x28 /r] s:AVX, t:DATAXFER, w:W|R, e:1
VMOVAPD Vx,Wx nil [vex m:1 p:1 l:x w:i 0x28 /r] s:AVX, t:DATAXFER, w:W|R, e:1
VMOVAPS Wx,Vx nil [vex m:1 p:0 l:x w:i 0x29 /r] s:AVX, t:DATAXFER, w:W|R, e:1
VMOVAPD Wx,Vx nil [vex m:1 p:1 l:x w:i 0x29 /r] s:AVX, t:DATAXFER, w:W|R, e:1
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
VCVTSI2SS Vss,Hss,Ey nil [vex m:1 p:2 l:i w:x 0x2A /r] s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64
VCVTSI2SD Vsd,Hsd,Ey nil [vex m:1 p:3 l:i w:x 0x2A /r] s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64
Initial commit.
2020-07-21 08:19:18 +00:00
VMOVNTPS Mx,Vx nil [vex m:1 p:0 l:x w:i 0x2B /r:mem] s:AVX, t:AVX, w:W|R, e:1
VMOVNTPD Mx,Vx nil [vex m:1 p:1 l:x w:i 0x2B /r:mem] s:AVX, t:AVX, w:W|R, e:1
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
VCVTTSS2SI Gy,Wss nil [vex m:1 p:2 l:i w:x 0x2C /r] s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
VCVTTSD2SI Gy,Wsd nil [vex m:1 p:3 l:i w:x 0x2C /r] s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
VCVTSS2SI Gy,Wss nil [vex m:1 p:2 l:i w:x 0x2D /r] s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
VCVTSD2SI Gy,Wsd nil [vex m:1 p:3 l:i w:x 0x2D /r] s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
Initial commit.
2020-07-21 08:19:18 +00:00
VUCOMISS Vss,Wss Fv [vex m:1 p:0 l:i w:i 0x2E /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
VUCOMISD Vsd,Wsd Fv [vex m:1 p:1 l:i w:i 0x2E /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
VCOMISS Vss,Wss Fv [vex m:1 p:0 l:i w:i 0x2F /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
VCOMISD Vsd,Wsd Fv [vex m:1 p:1 l:i w:i 0x2F /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
# 0x30 - 0x3F
# 0x40 - 0x4F
# Note: ALL these instructions will zero-extend the result into the destination, up to the max length of the mask reg.
KANDW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x41 /r:reg] s:AVX512F, t:KMASK, c:KAND, w:W|R|R, e:K20
KANDB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x41 /r:reg] s:AVX512DQ, t:KMASK, c:KAND, w:W|R|R, e:K20
KANDQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x41 /r:reg] s:AVX512BW, t:KMASK, c:KAND, w:W|R|R, e:K20
KANDD rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x41 /r:reg] s:AVX512BW, t:KMASK, c:KAND, w:W|R|R, e:K20
KANDNW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x42 /r:reg] s:AVX512F, t:KMASK, c:KANDN, w:W|R|R, e:K20
KANDNB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x42 /r:reg] s:AVX512DQ, t:KMASK, c:KANDN, w:W|R|R, e:K20
KANDNQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x42 /r:reg] s:AVX512BW, t:KMASK, c:KANDN, w:W|R|R, e:K20
KANDND rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x42 /r:reg] s:AVX512BW, t:KMASK, c:KANDN, w:W|R|R, e:K20
KORW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x45 /r:reg] s:AVX512F, t:KMASK, c:KOR, w:W|R|R, e:K20
KORB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x45 /r:reg] s:AVX512DQ, t:KMASK, c:KOR, w:W|R|R, e:K20
KORQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x45 /r:reg] s:AVX512BW, t:KMASK, c:KOR, w:W|R|R, e:K20
KORD rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x45 /r:reg] s:AVX512BW, t:KMASK, c:KOR, w:W|R|R, e:K20
KXNORW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x46 /r:reg] s:AVX512F, t:KMASK, c:KXNOR, w:W|R|R, e:K20
KXNORB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x46 /r:reg] s:AVX512DQ, t:KMASK, c:KXNOR, w:W|R|R, e:K20
KXNORQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x46 /r:reg] s:AVX512BW, t:KMASK, c:KXNOR, w:W|R|R, e:K20
KXNORD rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x46 /r:reg] s:AVX512BW, t:KMASK, c:KXNOR, w:W|R|R, e:K20
KXORW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x47 /r:reg] s:AVX512F, t:KMASK, c:KXOR, w:W|R|R, e:K20
KXORB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x47 /r:reg] s:AVX512DQ, t:KMASK, c:KXOR, w:W|R|R, e:K20
KXORQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x47 /r:reg] s:AVX512BW, t:KMASK, c:KXOR, w:W|R|R, e:K20
KXORD rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x47 /r:reg] s:AVX512BW, t:KMASK, c:KXOR, w:W|R|R, e:K20
KADDW rKw,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x4A /r:reg] s:AVX512DQ, t:KMASK, c:KADD, w:W|R|R, e:K20
KADDB rKb,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x4A /r:reg] s:AVX512DQ, t:KMASK, c:KADD, w:W|R|R, e:K20
KADDQ rKq,vKq,mKq nil [vex m:1 p:0 l:1 w:1 0x4A /r:reg] s:AVX512BW, t:KMASK, c:KADD, w:W|R|R, e:K20
KADDD rKd,vKd,mKd nil [vex m:1 p:1 l:1 w:1 0x4A /r:reg] s:AVX512BW, t:KMASK, c:KADD, w:W|R|R, e:K20
KMOVW rKw,Mw nil [vex m:1 p:0 l:0 w:0 0x90 /r:mem] s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K21
KMOVB rKb,Mb nil [vex m:1 p:1 l:0 w:0 0x90 /r:mem] s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K21
KMOVQ rKq,Mq nil [vex m:1 p:0 l:0 w:1 0x90 /r:mem] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21
KMOVD rKd,Md nil [vex m:1 p:1 l:0 w:1 0x90 /r:mem] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21
KMOVW rKw,mKw nil [vex m:1 p:0 l:0 w:0 0x90 /r:reg] s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVB rKb,mKb nil [vex m:1 p:1 l:0 w:0 0x90 /r:reg] s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVQ rKq,mKq nil [vex m:1 p:0 l:0 w:1 0x90 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVD rKd,mKd nil [vex m:1 p:1 l:0 w:1 0x90 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVW Mw,rKw nil [vex m:1 p:0 l:0 w:0 0x91 /r:mem] s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K21
KMOVB Mb,rKb nil [vex m:1 p:1 l:0 w:0 0x91 /r:mem] s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K21
KMOVQ Mq,rKq nil [vex m:1 p:0 l:0 w:1 0x91 /r:mem] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21
KMOVD Md,rKd nil [vex m:1 p:1 l:0 w:1 0x91 /r:mem] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21
KMOVW rKw,Ry nil [vex m:1 p:0 l:0 w:0 0x92 /r:reg] s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVB rKb,Ry nil [vex m:1 p:1 l:0 w:0 0x92 /r:reg] s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVQ rKq,Ry nil [vex m:1 p:3 l:0 w:1 0x92 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVD rKd,Ry nil [vex m:1 p:3 l:0 w:0 0x92 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVW Gy,mKw nil [vex m:1 p:0 l:0 w:0 0x93 /r:reg] s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVB Gy,mKb nil [vex m:1 p:1 l:0 w:0 0x93 /r:reg] s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVQ Gy,mKq nil [vex m:1 p:3 l:0 w:1 0x93 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20
KMOVD Gy,mKd nil [vex m:1 p:3 l:0 w:0 0x93 /r:reg] s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20
KMERGE2L1H rKw,mKw nil [vex m:1 p:0 l:0 w:0 0x48 /r:reg] s:UNKNOWN, t:UNKNOWN, c:KMERGE2L1H, w:W|R, e:K20
KMERGE2L1L rKw,mKw nil [vex m:1 p:0 l:0 w:0 0x49 /r:reg] s:UNKNOWN, t:UNKNOWN, c:KMERGE2L1L, w:W|R, e:K20
KUNPCKBW rKw,vKb,mKb nil [vex m:1 p:1 l:1 w:0 0x4B /r:reg] s:AVX512F, t:KMASK, c:KUNPCKBW, w:W|R|R, e:K20
KUNPCKWD rKd,vKw,mKw nil [vex m:1 p:0 l:1 w:0 0x4B /r:reg] s:AVX512BW, t:KMASK, c:KUNPCKWD, w:W|R|R, e:K20
KUNPCKDQ rKq,vKd,mKd nil [vex m:1 p:0 l:1 w:1 0x4B /r:reg] s:AVX512BW, t:KMASK, c:KUNPCKDQ, w:W|R|R, e:K20
KNOTW rKw,mKw nil [vex m:1 p:0 l:0 w:0 0x44 /r:reg] s:AVX512F, t:KMASK, c:KNOT, w:W|R, e:K20
KNOTB rKb,mKb nil [vex m:1 p:1 l:0 w:0 0x44 /r:reg] s:AVX512DQ, t:KMASK, c:KNOT, w:W|R, e:K20
KNOTQ rKq,mKq nil [vex m:1 p:0 l:0 w:1 0x44 /r:reg] s:AVX512BW, t:KMASK, c:KNOT, w:W|R, e:K20
KNOTD rKd,mKd nil [vex m:1 p:1 l:0 w:1 0x44 /r:reg] s:AVX512BW, t:KMASK, c:KNOT, w:W|R, e:K20
KORTESTW rKw,mKw Fv [vex m:1 p:0 l:0 w:0 0x98 /r:reg] s:AVX512F, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20
KORTESTB rKb,mKb Fv [vex m:1 p:1 l:0 w:0 0x98 /r:reg] s:AVX512DQ, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20
KORTESTQ rKq,mKq Fv [vex m:1 p:0 l:0 w:1 0x98 /r:reg] s:AVX512BW, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20
KORTESTD rKd,mKd Fv [vex m:1 p:1 l:0 w:1 0x98 /r:reg] s:AVX512BW, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20
KTESTW rKw,mKw nil [vex m:1 p:0 l:0 w:0 0x99 /r:reg] s:AVX512DQ, t:KMASK, c:KTEST, w:W|R, e:K20
KTESTB rKb,mKb nil [vex m:1 p:1 l:0 w:0 0x99 /r:reg] s:AVX512DQ, t:KMASK, c:KTEST, w:W|R, e:K20
KTESTQ rKq,mKq nil [vex m:1 p:0 l:0 w:1 0x99 /r:reg] s:AVX512BW, t:KMASK, c:KTEST, w:W|R, e:K20
KTESTD rKd,mKd nil [vex m:1 p:1 l:0 w:1 0x99 /r:reg] s:AVX512BW, t:KMASK, c:KTEST, w:W|R, e:K20
# 0x50 - 0x5F
VMOVMSKPS Gy,Ux nil [vex m:1 p:0 l:x w:i 0x50 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7
VMOVMSKPD Gy,Ux nil [vex m:1 p:1 l:x w:i 0x50 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7
VSQRTPS Vx,Wx nil [vex m:1 p:0 l:x w:i 0x51 /r] s:AVX, t:AVX, w:W|R, e:2
VSQRTPD Vx,Wx nil [vex m:1 p:1 l:x w:i 0x51 /r] s:AVX, t:AVX, w:W|R, e:2
VSQRTSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x51 /r] s:AVX, t:AVX, w:W|R|R, e:3
VSQRTSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x51 /r] s:AVX, t:AVX, w:W|R|R, e:3
VRSQRTPS Vx,Wx nil [vex m:1 p:0 l:x w:i 0x52 /r] s:AVX, t:AVX, w:W|R, e:4
VRSQRTSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x52 /r] s:AVX, t:AVX, w:W|R|R, e:5
VRCPPS Vps,Wps nil [vex m:1 p:0 l:x w:i 0x53 /r] s:AVX, t:AVX, w:W|R, e:4
VRCPSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x53 /r] s:AVX, t:AVX, w:W|R|R, e:5
VANDPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x54 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
VANDPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x54 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
VANDNPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x55 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
VANDNPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x55 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
VORPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x56 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
VORPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x56 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
VXORPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x57 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
VXORPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x57 /r] s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
VADDPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x58 /r] s:AVX, t:AVX, w:W|R|R, e:2
VADDPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x58 /r] s:AVX, t:AVX, w:W|R|R, e:2
VADDSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x58 /r] s:AVX, t:AVX, w:W|R|R, e:2
VADDSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x58 /r] s:AVX, t:AVX, w:W|R|R, e:2
VMULPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x59 /r] s:AVX, t:AVX, w:W|R|R, e:2
VMULPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x59 /r] s:AVX, t:AVX, w:W|R|R, e:2
VMULSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x59 /r] s:AVX, t:AVX, w:W|R|R, e:2
VMULSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x59 /r] s:AVX, t:AVX, w:W|R|R, e:2
VCVTPS2PD Vpd,Wq nil [vex m:1 p:0 l:0 w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R, e:2
VCVTPS2PD Vqq,Wdq nil [vex m:1 p:0 l:1 w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R, e:2
VCVTPD2PS Vdq,Wdq nil [vex m:1 p:1 l:0 w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R, e:2
VCVTPD2PS Vdq,Wqq nil [vex m:1 p:1 l:1 w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R, e:2
VCVTSS2SD Vsd,Hx,Wss nil [vex m:1 p:2 l:i w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R|R, e:3
VCVTSD2SS Vss,Hx,Wsd nil [vex m:1 p:3 l:i w:i 0x5A /r] s:AVX, t:CONVERT, w:W|R|R, e:3
VCVTDQ2PS Vps,Wps nil [vex m:1 p:0 l:x w:i 0x5B /r] s:AVX, t:CONVERT, w:W|R, e:2
VCVTPS2DQ Vps,Wps nil [vex m:1 p:1 l:x w:i 0x5B /r] s:AVX, t:CONVERT, w:W|R, e:2
VCVTTPS2DQ Vps,Wps nil [vex m:1 p:2 l:x w:i 0x5B /r] s:AVX, t:CONVERT, w:W|R, e:2
VSUBPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x5C /r] s:AVX, t:AVX, w:W|R|R, e:2
VSUBPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x5C /r] s:AVX, t:AVX, w:W|R|R, e:2
VSUBSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x5C /r] s:AVX, t:AVX, w:W|R|R, e:2
VSUBSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x5C /r] s:AVX, t:AVX, w:W|R|R, e:2
VMINPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x5D /r] s:AVX, t:AVX, w:W|R|R, e:2
VMINPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x5D /r] s:AVX, t:AVX, w:W|R|R, e:2
VMINSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x5D /r] s:AVX, t:AVX, w:W|R|R, e:2
VMINSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x5D /r] s:AVX, t:AVX, w:W|R|R, e:2
VDIVPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x5E /r] s:AVX, t:AVX, w:W|R|R, e:2
VDIVPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x5E /r] s:AVX, t:AVX, w:W|R|R, e:2
VDIVSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x5E /r] s:AVX, t:AVX, w:W|R|R, e:2
VDIVSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x5E /r] s:AVX, t:AVX, w:W|R|R, e:2
VMAXPS Vps,Hps,Wps nil [vex m:1 p:0 l:x w:i 0x5F /r] s:AVX, t:AVX, w:W|R|R, e:2
VMAXPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x5F /r] s:AVX, t:AVX, w:W|R|R, e:2
VMAXSS Vss,Hss,Wss nil [vex m:1 p:2 l:i w:i 0x5F /r] s:AVX, t:AVX, w:W|R|R, e:2
VMAXSD Vsd,Hsd,Wsd nil [vex m:1 p:3 l:i w:i 0x5F /r] s:AVX, t:AVX, w:W|R|R, e:2
# 0x60 - 0x6F
VPUNPCKLBW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x60 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPUNPCKLWD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x61 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPUNPCKLDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x62 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPACKSSWB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x63 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPCMPGTB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x64 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPCMPGTW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x65 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPCMPGTD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x66 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPACKUSWB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x67 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPUNPCKHBW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x68 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPUNPCKHWD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x69 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPUNPCKHDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6A /r] s:AVX, t:AVX, w:W|R|R, e:4
VPACKSSDW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6B /r] s:AVX, t:AVX, w:W|R|R, e:4
VPUNPCKLQDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6C /r] s:AVX, t:AVX, w:W|R|R, e:4
VPUNPCKHQDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6D /r] s:AVX, t:AVX, w:W|R|R, e:4
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
VMOVD Vdq,Ey nil [vex m:1 p:1 l:0 w:0 0x6E /r] s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64
VMOVQ Vdq,Ey nil [vex m:1 p:1 l:0 w:1 0x6E /r] s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64
Initial commit.
2020-07-21 08:19:18 +00:00
VMOVDQA Vx,Wx nil [vex m:1 p:1 l:x w:i 0x6F /r] s:AVX, t:DATAXFER, w:W|R, e:1
VMOVDQU Vx,Wx nil [vex m:1 p:2 l:x w:i 0x6F /r] s:AVX, t:DATAXFER, w:W|R, e:4
# 0x70 - 0x7F
VPSHUFD Vx,Wx,Ib nil [vex m:1 p:1 l:x w:i 0x70 /r ib] s:AVX, t:AVX, w:W|R|R, e:4
VPSHUFHW Vx,Wx,Ib nil [vex m:1 p:2 l:x w:i 0x70 /r ib] s:AVX, t:AVX, w:W|R|R, e:4
VPSHUFLW Vx,Wx,Ib nil [vex m:1 p:3 l:x w:i 0x70 /r ib] s:AVX, t:AVX, w:W|R|R, e:4
VPCMPEQB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x74 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPCMPEQW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x75 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPCMPEQD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x76 /r] s:AVX, t:AVX, w:W|R|R, e:4
VZEROUPPER nil BANK [vex m:1 p:0 l:0 0x77] s:AVX, t:AVX, w:W, e:8
VZEROALL nil BANK [vex m:1 p:0 l:1 0x77] s:AVX, t:AVX, w:W, e:8
VHADDPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x7C /r] s:AVX, t:AVX, w:W|R|R, e:2
VHADDPS Vps,Hps,Wps nil [vex m:1 p:3 l:x w:i 0x7C /r] s:AVX, t:AVX, w:W|R|R, e:2
VHSUBPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x7D /r] s:AVX, t:AVX, w:W|R|R, e:2
VHSUBPS Vps,Hps,Wps nil [vex m:1 p:3 l:x w:i 0x7D /r] s:AVX, t:AVX, w:W|R|R, e:2
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
VMOVD Ey,Vd nil [vex m:1 p:1 l:0 w:0 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64
VMOVQ Ey,Vq nil [vex m:1 p:1 l:0 w:1 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64
Initial commit.
2020-07-21 08:19:18 +00:00
VMOVQ Vdq,Wq nil [vex m:1 p:2 l:0 w:i 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVDQA Wx,Vx nil [vex m:1 p:1 l:x w:i 0x7F /r] s:AVX, t:DATAXFER, w:W|R, e:1
VMOVDQU Wx,Vx nil [vex m:1 p:2 l:x w:i 0x7F /r] s:AVX, t:DATAXFER, w:W|R, e:4
VPSRLW Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x71 /2:reg ib] s:AVX, t:AVX, w:W|R|R, e:7
VPSRAW Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x71 /4:reg ib] s:AVX, t:AVX, w:W|R|R, e:7
VPSLLW Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x71 /6:reg ib] s:AVX, t:AVX, w:W|R|R, e:7
VPSRLD Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x72 /2:reg ib] s:AVX, t:AVX, w:W|R|R, e:7
VPSRAD Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x72 /4:reg ib] s:AVX, t:AVX, w:W|R|R, e:7
VPSLLD Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x72 /6:reg ib] s:AVX, t:AVX, w:W|R|R, e:7
VPSRLQ Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x73 /2:reg ib] s:AVX, t:AVX, w:W|R|R, e:7
VPSRLDQ Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x73 /3:reg ib] s:AVX, t:AVX, w:W|R|R, e:7
VPSLLQ Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x73 /6:reg ib] s:AVX, t:AVX, w:W|R|R, e:7
VPSLLDQ Hx,Ux,Ib nil [vex m:1 p:1 l:x w:i 0x73 /7:reg ib] s:AVX, t:AVX, w:W|R|R, e:7
# 0x80 - 0x8F
# 0x90 - 0x9F
# 0xA0 - 0xAF
VLDMXCSR Md MXCSR [vex m:1 p:0 0xAE /2:mem] s:AVX, t:AVX, w:R|W, e:5
VSTMXCSR Md MXCSR [vex m:1 p:0 0xAE /3:mem] s:AVX, t:AVX, w:W|R, e:5
SPFLT Ry nil [vex m:1 p:3 0xAE /6:reg] s:UNKNOWN, t:UNKNOWN, w:R
DELAY Ry nil [vex m:1 p:2 0xAE /6:reg] s:UNKNOWN, t:UNKNOWN, w:R
CLEVICT0 M? nil [vex m:1 p:3 0xAE /7:mem] s:UNKNOWN, t:UNKNOWN, w:N
CLEVICT1 M? nil [vex m:1 p:2 0xAE /7:mem] s:UNKNOWN, t:UNKNOWN, w:N
# 0xB0 - 0xBF
# 0xC0 - 0xCF
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VCMPPS Vss,Hss,Wss,Ib nil [vex m:1 p:0 l:i w:i 0xC2 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3
Initial commit.
2020-07-21 08:19:18 +00:00
VCMPPD Vpd,Hpd,Wpd,Ib nil [vex m:1 p:1 l:x w:i 0xC2 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3
VCMPSS Vss,Hss,Wss,Ib nil [vex m:1 p:2 l:i w:i 0xC2 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3
VCMPSD Vsd,Hsd,Wsd,Ib nil [vex m:1 p:3 l:i w:i 0xC2 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:3
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VPINSRW Vdq,Hdq,Mw,Ib nil [vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib] s:AVX, t:AVX, w:W|R|R|R, e:5
VPINSRW Vdq,Hdq,Rd,Ib nil [vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib] s:AVX, t:AVX, w:W|R|R|R, e:5
VPEXTRW Gy,Udq,Ib nil [vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5
Initial commit.
2020-07-21 08:19:18 +00:00
VSHUFPS Vps,Hps,Wps,Ib nil [vex m:1 p:0 l:x w:i 0xC6 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4
VSHUFPD Vpd,Hpd,Wpd,Ib nil [vex m:1 p:1 l:x w:i 0xC6 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:4
# 0xD0 - 0xDF
VADDSUBPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0xD0 /r] s:AVX, t:AVX, w:W|R|R, e:2
VADDSUBPS Vps,Hps,Wps nil [vex m:1 p:3 l:x w:i 0xD0 /r] s:AVX, t:AVX, w:W|R|R, e:2
VPSRLW Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xD1 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSRLD Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xD2 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSRLQ Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xD3 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPADDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD4 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMULLW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD5 /r] s:AVX, t:AVX, w:W|R|R, e:4
VMOVQ Wq,Vdq nil [vex m:1 p:1 l:0 w:i 0xD6 /r] s:AVX, t:DATAXFER, w:W|R, e:5
VPMOVMSKB Gy,Ux nil [vex m:1 p:1 l:x w:i 0xD7 /r:reg] s:AVX, t:DATAXFER, w:W|R, e:7
VPSUBUSB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD8 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSUBUSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xD9 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMINUB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDA /r] s:AVX, t:AVX, w:W|R|R, e:4
VPAND Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDB /r] s:AVX, t:LOGICAL, w:W|R|R, e:4
VPADDUSB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDC /r] s:AVX, t:AVX, w:W|R|R, e:4
VPADDUSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDD /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMAXUB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDE /r] s:AVX, t:AVX, w:W|R|R, e:4
VPANDN Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xDF /r] s:AVX, t:LOGICAL, w:W|R|R, e:4
# 0xE0 - 0xEF
VPAVGB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE0 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSRAW Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xE1 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSRAD Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xE2 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPAVGW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE3 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMULHUW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE4 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMULHW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE5 /r] s:AVX, t:AVX, w:W|R|R, e:4
VCVTTPD2DQ Vdq,Wx nil [vex m:1 p:1 l:x w:i 0xE6 /r] s:AVX, t:CONVERT, w:W|R, e:2
VCVTDQ2PD Vdq,Wq nil [vex m:1 p:2 l:0 w:i 0xE6 /r] s:AVX, t:CONVERT, w:W|R, e:5
VCVTDQ2PD Vqq,Wdq nil [vex m:1 p:2 l:1 w:i 0xE6 /r] s:AVX, t:CONVERT, w:W|R, e:5
VCVTPD2DQ Vdq,Wx nil [vex m:1 p:3 l:x w:i 0xE6 /r] s:AVX, t:CONVERT, w:W|R, e:2
VMOVNTDQ Mx,Vx nil [vex m:1 p:1 l:x w:i 0xE7 /r:mem] s:AVX, t:AVX, w:W|R, e:1
VPSUBSB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE8 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSUBSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xE9 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMINSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xEA /r] s:AVX, t:AVX, w:W|R|R, e:4
VPOR Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xEB /r] s:AVX, t:LOGICAL, w:W|R|R, e:4
VPADDSB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xEC /r] s:AVX, t:AVX, w:W|R|R, e:4
VPADDSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xED /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMAXSW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xEE /r] s:AVX, t:AVX, w:W|R|R, e:4
VPXOR Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xEF /r] s:AVX, t:LOGICAL, w:W|R|R, e:4
# 0xF0 - 0xFF
VLDDQU Vx,Mx nil [vex m:1 p:3 l:x w:i 0xF0 /r:mem] s:AVX, t:AVX, w:W|R, e:4
VPSLLW Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xF1 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSLLD Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xF2 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSLLQ Vx,Hx,Wdq nil [vex m:1 p:1 l:x w:i 0xF3 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMULUDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xF4 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPMADDWD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xF5 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSADBW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xF6 /r] s:AVX, t:AVX, w:W|R|R, e:4
VMASKMOVDQU Vdq,Udq pDIdq [vex m:1 p:1 l:0 w:i 0xF7 /r:reg] s:AVX, t:AVX, w:R|R|W, e:4
VPSUBB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xF8 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSUBW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xF9 /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSUBD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xFA /r] s:AVX, t:AVX, w:W|R|R, e:4
VPSUBQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xFB /r] s:AVX, t:AVX, w:W|R|R, e:4
VPADDB Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xFC /r] s:AVX, t:AVX, w:W|R|R, e:4
VPADDW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xFD /r] s:AVX, t:AVX, w:W|R|R, e:4
VPADDD Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0xFE /r] s:AVX, t:AVX, w:W|R|R, e:4
Reference in New Issue Copy Permalink