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bddisasm/isagenerator/instructions/table_0F_38.dat

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Typo fixes in the instruction tables. Added a reference to the git repo in the documentation.
2020-07-21 13:38:09 +00:00
# Mnemonic Explicit Operands Implicit Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops
Initial commit.
2020-07-21 08:19:18 +00:00
#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# 0x00 - 0x0F
PSHUFB Pq,Qq nil [ NP 0x0F 0x38 0x00 /r] s:SSSE3, t:MMX, w:RW|R
PSHUFB Vx,Wx nil [ 0x66 0x0F 0x38 0x00 /r] s:SSSE3, t:SSE, w:RW|R, e:4
PHADDW Pq,Qq nil [ NP 0x0F 0x38 0x01 /r] s:SSSE3, t:MMX, w:RW|R
PHADDW Vx,Wx nil [ 0x66 0x0F 0x38 0x01 /r] s:SSSE3, t:SSE, w:RW|R, e:4
PHADDD Pq,Qq nil [ NP 0x0F 0x38 0x02 /r] s:SSSE3, t:MMX, w:RW|R
PHADDD Vx,Wx nil [ 0x66 0x0F 0x38 0x02 /r] s:SSSE3, t:SSE, w:RW|R, e:4
PHADDSW Pq,Qq nil [ NP 0x0F 0x38 0x03 /r] s:SSSE3, t:MMX, w:RW|R
PHADDSW Vx,Wx nil [ 0x66 0x0F 0x38 0x03 /r] s:SSSE3, t:SSE, w:RW|R, e:4
PMADDUBSW Pq,Qq nil [ NP 0x0F 0x38 0x04 /r] s:SSSE3, t:MMX, w:RW|R
PMADDUBSW Vx,Wx nil [ 0x66 0x0F 0x38 0x04 /r] s:SSSE3, t:SSE, w:RW|R, e:4
PHSUBW Pq,Qq nil [ NP 0x0F 0x38 0x05 /r] s:SSSE3, t:MMX, w:RW|R
PHSUBW Vx,Wx nil [ 0x66 0x0F 0x38 0x05 /r] s:SSSE3, t:SSE, w:RW|R, e:4
PHSUBD Pq,Qq nil [ NP 0x0F 0x38 0x06 /r] s:SSSE3, t:MMX, w:RW|R
PHSUBD Vx,Wx nil [ 0x66 0x0F 0x38 0x06 /r] s:SSSE3, t:SSE, w:RW|R, e:4
PHSUBSW Pq,Qq nil [ NP 0x0F 0x38 0x07 /r] s:SSSE3, t:MMX, w:RW|R
PHSUBSW Vx,Wx nil [ 0x66 0x0F 0x38 0x07 /r] s:SSSE3, t:SSE, w:RW|R, e:4
PSIGNB Pq,Qq nil [ NP 0x0F 0x38 0x08 /r] s:SSSE3, t:MMX, w:RW|R
PSIGNB Vx,Wx nil [ 0x66 0x0F 0x38 0x08 /r] s:SSSE3, t:SSE, w:RW|R, e:4
PSIGNW Pq,Qq nil [ NP 0x0F 0x38 0x09 /r] s:SSSE3, t:MMX, w:RW|R
PSIGNW Vx,Wx nil [ 0x66 0x0F 0x38 0x09 /r] s:SSSE3, t:SSE, w:RW|R, e:4
PSIGND Pq,Qq nil [ NP 0x0F 0x38 0x0A /r] s:SSSE3, t:MMX, w:RW|R
PSIGND Vx,Wx nil [ 0x66 0x0F 0x38 0x0A /r] s:SSSE3, t:SSE, w:RW|R, e:4
PMULHRSW Pq,Qq nil [ NP 0x0F 0x38 0x0B /r] s:SSSE3, t:MMX, w:RW|R
PMULHRSW Vx,Wx nil [ 0x66 0x0F 0x38 0x0B /r] s:SSSE3, t:SSE, w:RW|R, e:4
# 0x10 - 0x1F
PBLENDVB Vdq,Wdq XMM0 [ 0x66 0x0F 0x38 0x10 /r] s:SSE4, t:SSE, w:RW|R|R, e:4
BLENDVPS Vdq,Wdq XMM0 [ 0x66 0x0F 0x38 0x14 /r] s:SSE4, t:SSE, w:RW|R|R, e:4
BLENDVPD Vdq,Wdq XMM0 [ 0x66 0x0F 0x38 0x15 /r] s:SSE4, t:SSE, w:RW|R|R, e:4
PTEST Vdq,Wdq Fv [ 0x66 0x0F 0x38 0x17 /r] s:SSE4, t:SSE, w:R|R|W, f:CF=m|PF=0|AF=0|ZF=m|SF=0|OF=0, e:4
PABSB Pq,Qq nil [ NP 0x0F 0x38 0x1C /r] s:SSSE3, t:MMX, w:W|R
PABSB Vx,Wx nil [ 0x66 0x0F 0x38 0x1C /r] s:SSSE3, t:SSE, w:W|R, e:4
PABSW Pq,Qq nil [ NP 0x0F 0x38 0x1D /r] s:SSSE3, t:MMX, w:W|R
PABSW Vx,Wx nil [ 0x66 0x0F 0x38 0x1D /r] s:SSSE3, t:SSE, w:W|R, e:4
PABSD Pq,Qq nil [ NP 0x0F 0x38 0x1E /r] s:SSSE3, t:MMX, w:W|R
PABSD Vx,Wx nil [ 0x66 0x0F 0x38 0x1E /r] s:SSSE3, t:SSE, w:W|R, e:4
# 0x20 - 0x2F
PMOVSXBW Vdq,Wq nil [ 0x66 0x0F 0x38 0x20 /r] s:SSE4, t:SSE, w:W|R, e:5
PMOVSXBD Vdq,Wd nil [ 0x66 0x0F 0x38 0x21 /r] s:SSE4, t:SSE, w:W|R, e:5
PMOVSXBQ Vdq,Ww nil [ 0x66 0x0F 0x38 0x22 /r] s:SSE4, t:SSE, w:W|R, e:5
PMOVSXWD Vdq,Wq nil [ 0x66 0x0F 0x38 0x23 /r] s:SSE4, t:SSE, w:W|R, e:5
PMOVSXWQ Vdq,Wd nil [ 0x66 0x0F 0x38 0x24 /r] s:SSE4, t:SSE, w:W|R, e:5
PMOVSXDQ Vdq,Wq nil [ 0x66 0x0F 0x38 0x25 /r] s:SSE4, t:SSE, w:W|R, e:5
PMULDQ Vx,Wx nil [ 0x66 0x0F 0x38 0x28 /r] s:SSE4, t:SSE, w:RW|R, e:4
PCMPEQQ Vx,Wx nil [ 0x66 0x0F 0x38 0x29 /r] s:SSE4, t:SSE, w:RW|R, e:4
MOVNTDQA Vx,Mx nil [ 0x66 0x0F 0x38 0x2A /r:mem] s:SSE4, t:SSE, w:W|R, e:1
PACKUSDW Vx,Wx nil [ 0x66 0x0F 0x38 0x2B /r] s:SSE4, t:SSE, w:RW|R, e:4
# 0x30 - 0x3F
PMOVZXBW Vdq,Wq nil [ 0x66 0x0F 0x38 0x30 /r] s:SSE4, t:SSE, w:W|R, e:5
PMOVZXBD Vdq,Wd nil [ 0x66 0x0F 0x38 0x31 /r] s:SSE4, t:SSE, w:W|R, e:5
PMOVZXBQ Vdq,Ww nil [ 0x66 0x0F 0x38 0x32 /r] s:SSE4, t:SSE, w:W|R, e:5
PMOVZXWD Vdq,Wq nil [ 0x66 0x0F 0x38 0x33 /r] s:SSE4, t:SSE, w:W|R, e:5
PMOVZXWQ Vdq,Wd nil [ 0x66 0x0F 0x38 0x34 /r] s:SSE4, t:SSE, w:W|R, e:5
PMOVZXDQ Vdq,Wq nil [ 0x66 0x0F 0x38 0x35 /r] s:SSE4, t:SSE, w:W|R, e:5
PCMPGTQ Vx,Wx nil [ 0x66 0x0F 0x38 0x37 /r] s:SSE42, t:SSE, w:RW|R, e:4
PMINSB Vx,Wx nil [ 0x66 0x0F 0x38 0x38 /r] s:SSE4, t:SSE, w:RW|R, e:4
PMINSD Vx,Wx nil [ 0x66 0x0F 0x38 0x39 /r] s:SSE4, t:SSE, w:RW|R, e:4
PMINUW Vx,Wx nil [ 0x66 0x0F 0x38 0x3A /r] s:SSE4, t:SSE, w:RW|R, e:4
PMINUD Vx,Wx nil [ 0x66 0x0F 0x38 0x3B /r] s:SSE4, t:SSE, w:RW|R, e:4
PMAXSB Vx,Wx nil [ 0x66 0x0F 0x38 0x3C /r] s:SSE4, t:SSE, w:RW|R, e:4
PMAXSD Vx,Wx nil [ 0x66 0x0F 0x38 0x3D /r] s:SSE4, t:SSE, w:RW|R, e:4
PMAXUW Vx,Wx nil [ 0x66 0x0F 0x38 0x3E /r] s:SSE4, t:SSE, w:RW|R, e:4
PMAXUD Vx,Wx nil [ 0x66 0x0F 0x38 0x3F /r] s:SSE4, t:SSE, w:RW|R, e:4
# 0x40 - 0x4F
PMULLD Vx,Wx nil [ 0x66 0x0F 0x38 0x40 /r] s:SSE4, t:SSE, w:RW|R, e:4
PHMINPOSUW Vdq,Wdq nil [ 0x66 0x0F 0x38 0x41 /r] s:SSE4, t:SSE, w:W|R, e:4
# 0x50 - 0x5F
# 0x60 - 0x6F
# 0x70 - 0x7F
# 0x80 - 0x8F
INVEPT Gy,Mdq Fv [ 0x66 0x0F 0x38 0x80 /r:mem] s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL, m:VMXROOT
INVVPID Gy,Mdq Fv [ 0x66 0x0F 0x38 0x81 /r:mem] s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL, m:VMXROOT
INVPCID Gy,Mdq nil [ 0x66 0x0F 0x38 0x82 /r:mem] s:INVPCID, t:MISC, w:R|R, a:F64, m:KERNEL|NOV86
# 0x90 - 0x9F
# 0xA0 - 0xAF
# 0xB0 - 0xBF
# 0xC0 - 0xCF
SHA1NEXTE Vdq,Wdq nil [ NP 0x0F 0x38 0xC8 /r] s:SHA, t:SHA, w:RW|R, e:4
SHA1MSG1 Vdq,Wdq nil [ NP 0x0F 0x38 0xC9 /r] s:SHA, t:SHA, w:RW|R, e:4
SHA1MSG2 Vdq,Wdq nil [ NP 0x0F 0x38 0xCA /r] s:SHA, t:SHA, w:RW|R, e:4
SHA256RNDS2 Vdq,Wdq XMM0 [ NP 0x0F 0x38 0xCB /r] s:SHA, t:SHA, w:RW|R|R, e:4
SHA256MSG1 Vdq,Wdq nil [ NP 0x0F 0x38 0xCC /r] s:SHA, t:SHA, w:RW|R, e:4
SHA256MSG2 Vdq,Wdq nil [ NP 0x0F 0x38 0xCD /r] s:SHA, t:SHA, w:RW|R, e:4
GF2P8MULB Vdq,Wdq nil [ 0x66 0x0F 0x38 0xCF /r] s:GFNI, t:GFNI, w:RW|R, e:4
# 0xD0 - 0xDF
Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
2020-09-16 08:56:05 +00:00
AESENCWIDE128KL M384 XMM0-7,Fv [ 0xF3 0x0F 0x38 0xD8 /0:mem] s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL
AESDECWIDE128KL M384 XMM0-7,Fv [ 0xF3 0x0F 0x38 0xD8 /1:mem] s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL
AESENCWIDE256KL M512 XMM0-7,Fv [ 0xF3 0x0F 0x38 0xD8 /2:mem] s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL
AESDECWIDE256KL M512 XMM0-7,Fv [ 0xF3 0x0F 0x38 0xD8 /3:mem] s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL
Initial commit.
2020-07-21 08:19:18 +00:00
AESIMC Vdq,Wdq nil [ 0x66 0x0F 0x38 0xDB /r] s:AES, t:AES, w:W|R, e:4
AESENC Vdq,Wdq nil [ 0x66 0x0F 0x38 0xDC /r] s:AES, t:AES, w:RW|R, e:4
Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
2020-09-16 08:56:05 +00:00
AESENC128KL Vdq,M384 Fv [ 0xF3 0x0F 0x38 0xDC /r:mem] s:KL, t:AESKL, w:RW|R|W, f:AESKL
LOADIWKEY Vdq,Udq EAX,XMM0,Fv [ 0xF3 0x0F 0x38 0xDC /r:reg] s:KL, t:KL, w:R|R|R|R|W, f:AESKL, m:KERNEL
Initial commit.
2020-07-21 08:19:18 +00:00
AESENCLAST Vdq,Wdq nil [ 0x66 0x0F 0x38 0xDD /r] s:AES, t:AES, w:RW|R, e:4
Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
2020-09-16 08:56:05 +00:00
AESDEC128KL Vdq,M384 Fv [ 0xF3 0x0F 0x38 0xDD /r:mem] s:KL, t:AESKL, w:RW|R|W, f:AESKL
Initial commit.
2020-07-21 08:19:18 +00:00
AESDEC Vdq,Wdq nil [ 0x66 0x0F 0x38 0xDE /r] s:AES, t:AES, w:RW|R, e:4
Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
2020-09-16 08:56:05 +00:00
AESENC256KL Vdq,M512 Fv [ 0xF3 0x0F 0x38 0xDE /r:mem] s:KL, t:AESKL, w:RW|R|W, f:AESKL
Initial commit.
2020-07-21 08:19:18 +00:00
AESDECLAST Vdq,Wdq nil [ 0x66 0x0F 0x38 0xDF /r] s:AES, t:AES, w:RW|R, e:4
Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
2020-09-16 08:56:05 +00:00
AESDEC256KL Vdq,M512 Fv [ 0xF3 0x0F 0x38 0xDF /r:mem] s:KL, t:AESKL, w:RW|R|W, f:AESKL
Initial commit.
2020-07-21 08:19:18 +00:00
# 0xE0 - 0xEF
# 0xF0 - 0xFF
MOVBE Gv,Mv nil [ 0x0F 0x38 0xF0 /r:mem] s:MOVBE, t:DATAXFER, w:W|R
MOVBE Gv,Mv nil [ 0x66 0x0F 0x38 0xF0 /r:mem] s:MOVBE, t:DATAXFER, w:W|R, a:S66
CRC32 Gy,Eb nil [ 0xF2 0x0F 0x38 0xF0 /r] s:SSE42, t:SSE, w:RW|R
CRC32 Gy,Eb nil [ 0x66 0xF2 0x0F 0x38 0xF0 /r] s:SSE42, t:SSE, w:RW|R, a:S66
MOVBE Mv,Gv nil [ 0x0F 0x38 0xF1 /r:mem] s:MOVBE, t:DATAXFER, w:W|R
MOVBE Mv,Gv nil [ 0x66 0x0F 0x38 0xF1 /r:mem] s:MOVBE, t:DATAXFER, w:W|R, a:S66
CRC32 Gy,Ev nil [ 0xF2 0x0F 0x38 0xF1 /r] s:SSE42, t:SSE, w:RW|R
CRC32 Gy,Ev nil [ 0x66 0xF2 0x0F 0x38 0xF1 /r] s:SSE42, t:SSE, w:RW|R, a:S66
Use the documented byte granularity for cache-line accesses. Fixed CET CPUID feature flag - split into CET_SS and CET_IBT.
2020-07-21 21:47:46 +00:00
WRUSSD My,Gy nil [ 0x66 0x0F 0x38 0xF5 /r:mem] s:CET_SS, t:CET, c:WRUSS, a:SHS, w:W|R
WRUSSQ My,Gy nil [ rexw 0x66 0x0F 0x38 0xF5 /r:mem] s:CET_SS, t:CET, c:WRUSS, a:SHS, w:W|R
WRSSD My,Gy nil [ NP 0x0F 0x38 0xF6 /r:mem] s:CET_SS, t:CET, c:WRSS, a:SHS, w:W|R
WRSSQ My,Gy nil [ rexw NP 0x0F 0x38 0xF6 /r:mem] s:CET_SS, t:CET, c:WRSS, a:SHS, w:W|R
Initial commit.
2020-07-21 08:19:18 +00:00
ADCX Gy,Ey Fv [ 0x66 0x0F 0x38 0xF6 /r] s:ADX, t:ARITH, w:RW|R|RW, f:CF=m
ADOX Gy,Ey Fv [ 0xF3 0x0F 0x38 0xF6 /r] s:ADX, t:ARITH, w:RW|R|RW, f:OF=m
MOVDIR64B rMoq,Moq nil [ 0x66 0x0F 0x38 0xF8 /r:mem] s:MOVDIR64B, t:MOVDIR64B, w:W|R
ENQCMD rM?,Moq Fv [ 0xF2 0x0F 0x38 0xF8 /r:mem] s:ENQCMD, t:ENQCMD, w:W|R|W, f:ENQCMD
ENQCMDS rM?,Moq Fv [ 0xF3 0x0F 0x38 0xF8 /r:mem] s:ENQCMD, t:ENQCMD, w:W|R|W, f:ENQCMD
MOVDIRI My,Gy nil [ NP 0x0F 0x38 0xF9 /r:mem] s:MOVDIRI, t:MOVDIRI, w:W|R
Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
2020-09-16 08:56:05 +00:00
ENCODEKEY128 Gd,Rd XMM0,XMM0-2,XMM4-6,Fv [ 0xF3 0x0F 0x38 0xFA /r:reg] s:KL, t:AESKL, w:W|R|R|W|W|W, f:ZERO
ENCODEKEY256 Gd,Rd XMM0-1,XMM2-6,Fv [ 0xF3 0x0F 0x38 0xFB /r:reg] s:KL, t:AESKL, w:W|R|RW|W|W, f:ZERO
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