mirror of
https://github.com/trezor/trezor-firmware.git
synced 2024-11-09 17:10:17 +00:00
284 lines
11 KiB
C
284 lines
11 KiB
C
/*
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* This file is part of the Trezor project, https://trezor.io/
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*
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* Copyright (C) 2014 Pavol Rusnak <stick@satoshilabs.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/cm3/mpu.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/scb.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/rng.h>
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#include <libopencm3/stm32/spi.h>
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#include "layout.h"
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#include "rng.h"
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#include "util.h"
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uint32_t __stack_chk_guard;
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static inline void __attribute__((noreturn)) fault_handler(const char *line1) {
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layoutDialog(&bmp_icon_error, NULL, NULL, NULL, line1, "detected.", NULL,
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"Please unplug", "the device.", NULL);
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shutdown();
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}
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void __attribute__((noreturn)) __stack_chk_fail(void) {
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fault_handler("Stack smashing");
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}
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void nmi_handler(void) {
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// Clock Security System triggered NMI
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if ((RCC_CIR & RCC_CIR_CSSF) != 0) {
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fault_handler("Clock instability");
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}
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}
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void hard_fault_handler(void) { fault_handler("Hard fault"); }
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void mem_manage_handler(void) { fault_handler("Memory fault"); }
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void setup(void) {
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// set SCB_CCR STKALIGN bit to make sure 8-byte stack alignment on exception
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// entry is in effect. This is not strictly necessary for the current Trezor
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// system. This is here to comply with guidance from section 3.3.3 "Binary
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// compatibility with other Cortex processors" of the ARM Cortex-M3 Processor
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// Technical Reference Manual. According to section 4.4.2 and 4.4.7 of the
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// "STM32F10xxx/20xxx/21xxx/L1xxxx Cortex-M3 programming manual", STM32F2
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// series MCUs are r2p0 and always have this bit set on reset already.
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SCB_CCR |= SCB_CCR_STKALIGN;
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// setup clock
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struct rcc_clock_scale clock = rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_120MHZ];
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rcc_clock_setup_hse_3v3(&clock);
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// enable GPIO clock - A (oled), B(oled), C (buttons)
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rcc_periph_clock_enable(RCC_GPIOA);
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rcc_periph_clock_enable(RCC_GPIOB);
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rcc_periph_clock_enable(RCC_GPIOC);
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// enable SPI clock
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rcc_periph_clock_enable(RCC_SPI1);
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// enable RNG
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rcc_periph_clock_enable(RCC_RNG);
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RNG_CR |= RNG_CR_RNGEN;
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// to be extra careful and heed the STM32F205xx Reference manual,
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// Section 20.3.1 we don't use the first random number generated after setting
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// the RNGEN bit in setup
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random32();
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// enable CSS (Clock Security System)
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RCC_CR |= RCC_CR_CSSON;
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// set GPIO for buttons
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gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, GPIO2 | GPIO5);
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// set GPIO for OLED display
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gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO4);
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gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0 | GPIO1);
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// enable SPI 1 for OLED display
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO7);
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gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO7);
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// spi_disable_crc(SPI1);
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spi_init_master(
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SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
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SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
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spi_enable_ss_output(SPI1);
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// spi_enable_software_slave_management(SPI1);
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// spi_set_nss_high(SPI1);
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// spi_clear_mode_fault(SPI1);
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spi_enable(SPI1);
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// enable OTG_FS
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO10);
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11 | GPIO12);
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gpio_set_af(GPIOA, GPIO_AF10, GPIO10 | GPIO11 | GPIO12);
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// enable OTG FS clock
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rcc_periph_clock_enable(RCC_OTGFS);
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// clear USB OTG_FS peripheral dedicated RAM
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memset_reg((void *)0x50020000, (void *)0x50020500, 0);
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}
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void setupApp(void) {
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// for completeness, disable RNG peripheral interrupts for old bootloaders
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// that had enabled them in RNG control register (the RNG interrupt was never
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// enabled in the NVIC)
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RNG_CR &= ~RNG_CR_IE;
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// the static variables in random32 are separate between the bootloader and
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// firmware. therefore, they need to be initialized here so that we can be
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// sure to avoid dupes. this is to try to comply with STM32F205xx Reference
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// manual - Section 20.3.1: "Each subsequent generated random number has to be
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// compared with the previously generated number. The test fails if any two
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// compared numbers are equal (continuous random number generator test)."
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random32();
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// enable CSS (Clock Security System)
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RCC_CR |= RCC_CR_CSSON;
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// hotfix for old bootloader
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gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO9);
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spi_init_master(
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SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
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SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO10);
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gpio_set_af(GPIOA, GPIO_AF10, GPIO10);
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}
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#define MPU_RASR_SIZE_32B (0x04UL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_1KB (0x09UL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_128KB (0x10UL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_256KB (0x11UL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_512KB (0x12UL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_1MB (0x13UL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_LSB)
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// http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABDJJGF.html
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#define MPU_RASR_ATTR_FLASH (MPU_RASR_ATTR_C)
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#define MPU_RASR_ATTR_SRAM (MPU_RASR_ATTR_C | MPU_RASR_ATTR_S)
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#define MPU_RASR_ATTR_PERIPH (MPU_RASR_ATTR_B | MPU_RASR_ATTR_S)
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#define FLASH_BASE (0x08000000U)
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#define SRAM_BASE (0x20000000U)
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void mpu_config_off(void) {
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// Disable MPU
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MPU_CTRL = 0;
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__asm__ volatile("dsb");
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__asm__ volatile("isb");
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}
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void mpu_config_bootloader(void) {
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// Disable MPU
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MPU_CTRL = 0;
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// Note: later entries overwrite previous ones
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// Everything (0x00000000 - 0xFFFFFFFF, 4 GiB, read-write)
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MPU_RBAR = 0 | MPU_RBAR_VALID | (0 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_4GB |
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MPU_RASR_ATTR_AP_PRW_URW;
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// Flash (0x8007FE0 - 0x08007FFF, 32 B, no-access)
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MPU_RBAR =
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(FLASH_BASE + 0x7FE0) | MPU_RBAR_VALID | (1 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_32B |
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MPU_RASR_ATTR_AP_PNO_UNO;
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// SRAM (0x20000000 - 0x2001FFFF, read-write, execute never)
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MPU_RBAR = SRAM_BASE | MPU_RBAR_VALID | (2 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_SRAM | MPU_RASR_SIZE_128KB |
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MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// Peripherals (0x40000000 - 0x4001FFFF, read-write, execute never)
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MPU_RBAR = PERIPH_BASE | MPU_RBAR_VALID | (3 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_PERIPH | MPU_RASR_SIZE_128KB |
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MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// Peripherals (0x40020000 - 0x40023FFF, read-write, execute never)
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MPU_RBAR = 0x40020000 | MPU_RBAR_VALID | (4 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_PERIPH | MPU_RASR_SIZE_16KB |
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MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// Don't enable DMA controller access
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// Peripherals (0x50000000 - 0x5007ffff, read-write, execute never)
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MPU_RBAR = 0x50000000 | MPU_RBAR_VALID | (5 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_PERIPH | MPU_RASR_SIZE_512KB |
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MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// Enable MPU
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MPU_CTRL = MPU_CTRL_ENABLE | MPU_CTRL_HFNMIENA;
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// Enable memory fault handler
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SCB_SHCSR |= SCB_SHCSR_MEMFAULTENA;
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__asm__ volatile("dsb");
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__asm__ volatile("isb");
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}
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// Never use in bootloader! Disables access to PPB (including MPU, NVIC, SCB)
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void mpu_config_firmware(void) {
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#if PRODUCTION || BOOTLOADER_QA
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// Disable MPU
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MPU_CTRL = 0;
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// Note: later entries overwrite previous ones
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// Flash (0x08000000 - 0x0807FFFF, 1 MiB, read-only)
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MPU_RBAR = FLASH_BASE | MPU_RBAR_VALID | (0 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_1MB |
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MPU_RASR_ATTR_AP_PRO_URO;
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// Metadata in Flash is read-write when unlocked
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// (0x08008000 - 0x0800FFFF, 32 KiB, read-write, execute never)
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MPU_RBAR =
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(FLASH_BASE + 0x8000) | MPU_RBAR_VALID | (1 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_FLASH | MPU_RASR_SIZE_32KB |
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MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// SRAM (0x20000000 - 0x2001FFFF, read-write, execute never)
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MPU_RBAR = SRAM_BASE | MPU_RBAR_VALID | (2 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_SRAM | MPU_RASR_SIZE_128KB |
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MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// Peripherals (0x40000000 - 0x4001FFFF, read-write, execute never)
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MPU_RBAR = PERIPH_BASE | MPU_RBAR_VALID | (3 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_PERIPH | MPU_RASR_SIZE_128KB |
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MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// Peripherals (0x40020000 - 0x40023FFF, read-write, execute never)
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MPU_RBAR = 0x40020000 | MPU_RBAR_VALID | (4 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_PERIPH | MPU_RASR_SIZE_16KB |
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MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// Flash controller is protected
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// (0x40023C00 - 0x40023FFF, privileged read-write, user no, execute never)
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MPU_RBAR = 0x40023c00 | MPU_RBAR_VALID | (5 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_PERIPH | MPU_RASR_SIZE_1KB |
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MPU_RASR_ATTR_AP_PRW_UNO | MPU_RASR_ATTR_XN;
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// Don't enable DMA controller access
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// Peripherals (0x50000000 - 0x5007ffff, read-write, execute never)
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MPU_RBAR = 0x50000000 | MPU_RBAR_VALID | (6 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_PERIPH | MPU_RASR_SIZE_512KB |
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MPU_RASR_ATTR_AP_PRW_URW | MPU_RASR_ATTR_XN;
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// SYSCFG_* registers are disabled
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// (0x40013800 - 0x40013BFF, read-only, execute never)
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MPU_RBAR = 0x40013800 | MPU_RBAR_VALID | (7 << MPU_RBAR_REGION_LSB);
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MPU_RASR = MPU_RASR_ENABLE | MPU_RASR_ATTR_PERIPH | MPU_RASR_SIZE_1KB |
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MPU_RASR_ATTR_AP_PRO_URO | MPU_RASR_ATTR_XN;
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// Enable MPU
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MPU_CTRL = MPU_CTRL_ENABLE | MPU_CTRL_HFNMIENA;
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// Enable memory fault handler
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SCB_SHCSR |= SCB_SHCSR_MEMFAULTENA;
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__asm__ volatile("dsb");
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__asm__ volatile("isb");
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// Switch to unprivileged software execution to prevent access to MPU
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set_mode_unprivileged();
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#endif
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}
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