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305 lines
10 KiB
305 lines
10 KiB
/*
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* This file is part of the Micro Python project, http://micropython.org/
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*
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* Original template from ST Cube library. See below for header.
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/**
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******************************************************************************
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* @file Templates/Src/stm32f4xx_it.c
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* @author MCD Application Team
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* @version V1.0.1
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* @date 26-February-2014
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* @brief Main Interrupt Service Routines.
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* This file provides template for all exceptions handler and
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* peripherals interrupt service routine.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#include STM32_HAL_H
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#include "pendsv.h"
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#include "gccollect.h"
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#include "display.h"
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#define IRQ_ENTER(irq)
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#define IRQ_EXIT(irq)
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extern void __fatal_error(const char*);
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/******************************************************************************/
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/* Cortex-M4 Processor Exceptions Handlers */
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/******************************************************************************/
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// Set the following to 1 to get some more information on the Hard Fault
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// More information about decoding the fault registers can be found here:
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// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0646a/Cihdjcfc.html
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static char *fmt_hex(uint32_t val, char *buf) {
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const char *hexDig = "0123456789abcdef";
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buf[0] = hexDig[(val >> 28) & 0x0f];
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buf[1] = hexDig[(val >> 24) & 0x0f];
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buf[2] = hexDig[(val >> 20) & 0x0f];
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buf[3] = hexDig[(val >> 16) & 0x0f];
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buf[4] = hexDig[(val >> 12) & 0x0f];
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buf[5] = hexDig[(val >> 8) & 0x0f];
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buf[6] = hexDig[(val >> 4) & 0x0f];
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buf[7] = hexDig[(val >> 0) & 0x0f];
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buf[8] = '\0';
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return buf;
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}
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static void print_reg(const char *label, uint32_t val) {
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char hexStr[9];
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display_print(label, -1);
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display_print(fmt_hex(val, hexStr), -1);
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display_print("\n", 1);
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}
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static void print_hex_hex(const char *label, uint32_t val1, uint32_t val2) {
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char hex_str[9];
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display_print(label, -1 );
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display_print(fmt_hex(val1, hex_str), -1);
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display_print(" ", 2);
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display_print(fmt_hex(val2, hex_str), -1);
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display_print("\n", 1);
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}
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// The ARMv7M Architecture manual (section B.1.5.6) says that upon entry
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// to an exception, that the registers will be in the following order on the
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// stack: R0, R1, R2, R3, R12, LR, PC, XPSR
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typedef struct {
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uint32_t r0, r1, r2, r3, r12, lr, pc, xpsr;
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} ExceptionRegisters_t;
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int pyb_hard_fault_debug = 1;
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void HardFault_C_Handler(ExceptionRegisters_t *regs) {
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if (!pyb_hard_fault_debug) {
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NVIC_SystemReset();
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}
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// We need to disable the USB so it doesn't try to write data out on
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// the VCP and then block indefinitely waiting for the buffer to drain.
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// pyb_usb_flags = 0;
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display_print("HardFault\n", -1);
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print_reg("R0 ", regs->r0);
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print_reg("R1 ", regs->r1);
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print_reg("R2 ", regs->r2);
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print_reg("R3 ", regs->r3);
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print_reg("R12 ", regs->r12);
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print_reg("SP ", (uint32_t)regs);
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print_reg("LR ", regs->lr);
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print_reg("PC ", regs->pc);
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print_reg("XPSR ", regs->xpsr);
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uint32_t cfsr = SCB->CFSR;
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print_reg("HFSR ", SCB->HFSR);
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print_reg("CFSR ", cfsr);
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if (cfsr & 0x80) {
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print_reg("MMFAR ", SCB->MMFAR);
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}
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if (cfsr & 0x8000) {
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print_reg("BFAR ", SCB->BFAR);
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}
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if ((void*)&_ram_start <= (void*)regs && (void*)regs < (void*)&_ram_end) {
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display_print("Stack:\n", -1);
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uint32_t *stack_top = &_estack;
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if ((void*)regs < (void*)&_heap_end) {
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// stack not in static stack area so limit the amount we print
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stack_top = (uint32_t*)regs + 32;
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}
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for (uint32_t *sp = (uint32_t*)regs; sp < stack_top; ++sp) {
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print_hex_hex(" ", (uint32_t)sp, *sp);
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}
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}
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/* Go to infinite loop when Hard Fault exception occurs */
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while (1) {
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__fatal_error("HardFault");
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}
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}
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// Naked functions have no compiler generated gunk, so are the best thing to
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// use for asm functions.
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__attribute__((naked))
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void HardFault_Handler(void) {
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// From the ARMv7M Architecture Reference Manual, section B.1.5.6
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// on entry to the Exception, the LR register contains, amongst other
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// things, the value of CONTROL.SPSEL. This can be found in bit 3.
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//
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// If CONTROL.SPSEL is 0, then the exception was stacked up using the
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// main stack pointer (aka MSP). If CONTROL.SPSEL is 1, then the exception
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// was stacked up using the process stack pointer (aka PSP).
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__asm volatile(
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" tst lr, #4 \n" // Test Bit 3 to see which stack pointer we should use.
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" ite eq \n" // Tell the assembler that the nest 2 instructions are if-then-else
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" mrseq r0, msp \n" // Make R0 point to main stack pointer
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" mrsne r0, psp \n" // Make R0 point to process stack pointer
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" b HardFault_C_Handler \n" // Off to C land
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);
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}
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/**
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* @brief This function handles NMI exception.
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* @param None
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* @retval None
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*/
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void NMI_Handler(void) {
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}
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/**
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* @brief This function handles Memory Manage exception.
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* @param None
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* @retval None
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*/
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void MemManage_Handler(void) {
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/* Go to infinite loop when Memory Manage exception occurs */
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while (1) {
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__fatal_error("MemManage");
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}
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}
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/**
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* @brief This function handles Bus Fault exception.
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* @param None
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* @retval None
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*/
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void BusFault_Handler(void) {
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/* Go to infinite loop when Bus Fault exception occurs */
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while (1) {
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__fatal_error("BusFault");
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}
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}
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/**
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* @brief This function handles Usage Fault exception.
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* @param None
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* @retval None
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*/
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void UsageFault_Handler(void) {
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/* Go to infinite loop when Usage Fault exception occurs */
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while (1) {
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__fatal_error("UsageFault");
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}
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}
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/**
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* @brief This function handles SVCall exception.
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* @param None
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* @retval None
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*/
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void SVC_Handler(void) {
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}
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/**
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* @brief This function handles Debug Monitor exception.
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* @param None
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* @retval None
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*/
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void DebugMon_Handler(void) {
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}
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/**
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* @brief This function handles PendSVC exception.
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* @param None
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* @retval None
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*/
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void PendSV_Handler(void) {
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pendsv_isr_handler();
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}
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/**
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* @brief This function handles SysTick Handler.
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* @param None
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* @retval None
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*/
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void SysTick_Handler(void) {
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// Instead of calling HAL_IncTick we do the increment here of the counter.
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// This is purely for efficiency, since SysTick is called 1000 times per
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// second at the highest interrupt priority.
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// Note: we don't need uwTick to be declared volatile here because this is
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// the only place where it can be modified, and the code is more efficient
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// without the volatile specifier.
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extern uint32_t uwTick;
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uwTick += 1;
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// Read the systick control regster. This has the side effect of clearing
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// the COUNTFLAG bit, which makes the logic in sys_tick_get_microseconds
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// work properly.
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SysTick->CTRL;
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// Right now we have the storage and DMA controllers to process during
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// this interrupt and we use custom dispatch handlers. If this needs to
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// be generalised in the future then a dispatch table can be used as
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// follows: ((void(*)(void))(systick_dispatch[uwTick & 0xf]))();
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// if (STORAGE_IDLE_TICK(uwTick)) {
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// NVIC->STIR = FLASH_IRQn;
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// }
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// if (DMA_IDLE_ENABLED() && DMA_IDLE_TICK(uwTick)) {
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// dma_idle_handler(uwTick);
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// }
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}
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