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https://github.com/trezor/trezor-firmware.git
synced 2025-01-25 14:50:57 +00:00
71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
#include STM32_HAL_H
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#include "lowlevel.h"
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#define WANTED_WRP (OB_WRP_SECTOR_0 | OB_WRP_SECTOR_1 | OB_WRP_SECTOR_2)
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#define WANTED_RDP (OB_RDP_LEVEL_2)
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#define WANTED_BOR (OB_BOR_LEVEL3)
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void flash_set_option_bytes(void)
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{
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FLASH_OBProgramInitTypeDef opts;
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HAL_FLASHEx_OBGetConfig(&opts);
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opts.OptionType = 0;
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if (opts.WRPSector != WANTED_WRP) {
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opts.OptionType = OPTIONBYTE_WRP;
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opts.WRPState = OB_WRPSTATE_ENABLE;
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opts.WRPSector = WANTED_WRP;
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opts.Banks = FLASH_BANK_1;
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}
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if (opts.RDPLevel != WANTED_RDP) {
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opts.OptionType = OPTIONBYTE_RDP;
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opts.RDPLevel = WANTED_RDP;
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}
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if (opts.BORLevel != WANTED_BOR) {
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opts.OptionType = OPTIONBYTE_BOR;
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opts.BORLevel = WANTED_BOR;
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}
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if (opts.OptionType != 0) {
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HAL_FLASHEx_OBProgram(&opts);
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}
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}
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bool flash_check_option_bytes(void)
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{
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return
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((FLASH->OPTCR & FLASH_OPTCR_nWRP) == (FLASH_OPTCR_nWRP_0 | FLASH_OPTCR_nWRP_1 | FLASH_OPTCR_nWRP_2)) &&
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((FLASH->OPTCR & FLASH_OPTCR_RDP) == FLASH_OPTCR_RDP_2) &&
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((FLASH->OPTCR & FLASH_OPTCR_BOR_LEV) == (FLASH_OPTCR_BOR_LEV_0 | FLASH_OPTCR_BOR_LEV_1));
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}
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void periph_init(void)
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{
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// STM32F4xx HAL library initialization:
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// - configure the Flash prefetch, instruction and data caches
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// - configure the Systick to generate an interrupt each 1 msec
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// - set NVIC Group Priority to 4
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// - global MSP (MCU Support Package) initialization
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HAL_Init();
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// Enable GPIO clocks
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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// Clear the reset flags
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PWR->CR |= PWR_CR_CSBF;
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RCC->CSR |= RCC_CSR_RMVF;
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// Enable CPU ticks
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; // Enable DWT
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DWT->CYCCNT = 0; // Reset Cycle Count Register
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DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; // Enable Cycle Count Register
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}
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