mirror of
https://github.com/trezor/trezor-firmware.git
synced 2024-11-27 01:48:17 +00:00
306 lines
13 KiB
C
306 lines
13 KiB
C
// clang-format off
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2015-2019 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <string.h>
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#include <stdint.h>
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#include "dma.h"
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#include "irq.h"
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#include "systick.h"
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#include "supervise.h"
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#define DMA_IDLE_ENABLED() (dma_idle.enabled != 0)
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#define DMA_SYSTICK_LOG2 (3)
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#define DMA_SYSTICK_MASK ((1 << DMA_SYSTICK_LOG2) - 1)
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#define DMA_IDLE_TICK_MAX (8) // 8*8 = 64 msec
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#define DMA_IDLE_TICK(tick) (((tick) & ~(SYSTICK_DISPATCH_NUM_SLOTS - 1) & DMA_SYSTICK_MASK) == 0)
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typedef enum {
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dma_id_not_defined=-1,
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dma_id_0,
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dma_id_1,
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dma_id_2,
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dma_id_3,
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dma_id_4,
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dma_id_5,
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dma_id_6,
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dma_id_7,
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dma_id_8,
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dma_id_9,
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dma_id_10,
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dma_id_11,
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dma_id_12,
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dma_id_13,
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dma_id_14,
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dma_id_15,
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} dma_id_t;
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typedef union {
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uint16_t enabled; // Used to test if both counters are == 0
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uint8_t counter[2];
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} dma_idle_count_t;
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struct _dma_descr_t {
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DMA_Stream_TypeDef *instance;
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uint32_t sub_instance;
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dma_id_t id;
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const DMA_InitTypeDef *init;
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};
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// Parameters to dma_init() for SDIO tx and rx.
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static const DMA_InitTypeDef dma_init_struct_sdio = {
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.Channel = 0,
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.Direction = 0,
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.PeriphInc = DMA_PINC_DISABLE,
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.MemInc = DMA_MINC_ENABLE,
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.PeriphDataAlignment = DMA_PDATAALIGN_WORD,
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.MemDataAlignment = DMA_MDATAALIGN_WORD,
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.Mode = DMA_PFCTRL,
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.Priority = DMA_PRIORITY_VERY_HIGH,
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.FIFOMode = DMA_FIFOMODE_ENABLE,
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.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL,
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.MemBurst = DMA_MBURST_INC4,
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.PeriphBurst = DMA_PBURST_INC4,
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};
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#define NCONTROLLERS (2)
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#define NSTREAMS_PER_CONTROLLER (8)
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#define NSTREAM (NCONTROLLERS * NSTREAMS_PER_CONTROLLER)
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#define DMA_SUB_INSTANCE_AS_UINT8(dma_channel) (((dma_channel) & DMA_SxCR_CHSEL) >> 25)
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#define DMA1_ENABLE_MASK (0x00ff) // Bits in dma_enable_mask corresponding to DMA1
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#define DMA2_ENABLE_MASK (0xff00) // Bits in dma_enable_mask corresponding to DMA2
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const dma_descr_t dma_SDIO_0 = { DMA2_Stream3, DMA_CHANNEL_4, dma_id_11, &dma_init_struct_sdio };
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static const uint8_t dma_irqn[NSTREAM] = {
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DMA1_Stream0_IRQn,
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DMA1_Stream1_IRQn,
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DMA1_Stream2_IRQn,
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DMA1_Stream3_IRQn,
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DMA1_Stream4_IRQn,
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DMA1_Stream5_IRQn,
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DMA1_Stream6_IRQn,
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DMA1_Stream7_IRQn,
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DMA2_Stream0_IRQn,
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DMA2_Stream1_IRQn,
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DMA2_Stream2_IRQn,
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DMA2_Stream3_IRQn,
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DMA2_Stream4_IRQn,
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DMA2_Stream5_IRQn,
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DMA2_Stream6_IRQn,
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DMA2_Stream7_IRQn,
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};
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static DMA_HandleTypeDef *dma_handle[NSTREAM] = {NULL};
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static uint8_t dma_last_sub_instance[NSTREAM];
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static volatile uint32_t dma_enable_mask = 0;
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volatile dma_idle_count_t dma_idle;
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#define DMA_INVALID_CHANNEL 0xff // Value stored in dma_last_channel which means invalid
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#define DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0)
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#define DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0)
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void DMA1_Stream0_IRQHandler(void) { IRQ_ENTER(DMA1_Stream0_IRQn); if (dma_handle[dma_id_0] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_0]); } IRQ_EXIT(DMA1_Stream0_IRQn); }
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void DMA1_Stream1_IRQHandler(void) { IRQ_ENTER(DMA1_Stream1_IRQn); if (dma_handle[dma_id_1] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_1]); } IRQ_EXIT(DMA1_Stream1_IRQn); }
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void DMA1_Stream2_IRQHandler(void) { IRQ_ENTER(DMA1_Stream2_IRQn); if (dma_handle[dma_id_2] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_2]); } IRQ_EXIT(DMA1_Stream2_IRQn); }
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void DMA1_Stream3_IRQHandler(void) { IRQ_ENTER(DMA1_Stream3_IRQn); if (dma_handle[dma_id_3] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_3]); } IRQ_EXIT(DMA1_Stream3_IRQn); }
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void DMA1_Stream4_IRQHandler(void) { IRQ_ENTER(DMA1_Stream4_IRQn); if (dma_handle[dma_id_4] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_4]); } IRQ_EXIT(DMA1_Stream4_IRQn); }
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void DMA1_Stream5_IRQHandler(void) { IRQ_ENTER(DMA1_Stream5_IRQn); if (dma_handle[dma_id_5] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_5]); } IRQ_EXIT(DMA1_Stream5_IRQn); }
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void DMA1_Stream6_IRQHandler(void) { IRQ_ENTER(DMA1_Stream6_IRQn); if (dma_handle[dma_id_6] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_6]); } IRQ_EXIT(DMA1_Stream6_IRQn); }
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void DMA1_Stream7_IRQHandler(void) { IRQ_ENTER(DMA1_Stream7_IRQn); if (dma_handle[dma_id_7] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_7]); } IRQ_EXIT(DMA1_Stream7_IRQn); }
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void DMA2_Stream0_IRQHandler(void) { IRQ_ENTER(DMA2_Stream0_IRQn); if (dma_handle[dma_id_8] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_8]); } IRQ_EXIT(DMA2_Stream0_IRQn); }
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void DMA2_Stream1_IRQHandler(void) { IRQ_ENTER(DMA2_Stream1_IRQn); if (dma_handle[dma_id_9] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_9]); } IRQ_EXIT(DMA2_Stream1_IRQn); }
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void DMA2_Stream2_IRQHandler(void) { IRQ_ENTER(DMA2_Stream2_IRQn); if (dma_handle[dma_id_10] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_10]); } IRQ_EXIT(DMA2_Stream2_IRQn); }
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void DMA2_Stream3_IRQHandler(void) { IRQ_ENTER(DMA2_Stream3_IRQn); if (dma_handle[dma_id_11] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_11]); } IRQ_EXIT(DMA2_Stream3_IRQn); }
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void DMA2_Stream4_IRQHandler(void) { IRQ_ENTER(DMA2_Stream4_IRQn); if (dma_handle[dma_id_12] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_12]); } IRQ_EXIT(DMA2_Stream4_IRQn); }
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void DMA2_Stream5_IRQHandler(void) { IRQ_ENTER(DMA2_Stream5_IRQn); if (dma_handle[dma_id_13] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_13]); } IRQ_EXIT(DMA2_Stream5_IRQn); }
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void DMA2_Stream6_IRQHandler(void) { IRQ_ENTER(DMA2_Stream6_IRQn); if (dma_handle[dma_id_14] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_14]); } IRQ_EXIT(DMA2_Stream6_IRQn); }
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void DMA2_Stream7_IRQHandler(void) { IRQ_ENTER(DMA2_Stream7_IRQn); if (dma_handle[dma_id_15] != NULL) { HAL_DMA_IRQHandler(dma_handle[dma_id_15]); } IRQ_EXIT(DMA2_Stream7_IRQn); }
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static void dma_idle_handler(uint32_t tick);
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// Resets the idle counter for the DMA controller associated with dma_id.
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static void dma_tickle(dma_id_t dma_id) {
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dma_idle.counter[(dma_id < NSTREAMS_PER_CONTROLLER) ? 0 : 1] = 1;
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systick_enable_dispatch(SYSTICK_DISPATCH_DMA, dma_idle_handler);
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}
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static void dma_enable_clock(dma_id_t dma_id) {
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// We don't want dma_tick_handler() to turn off the clock right after we
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// enable it, so we need to mark the channel in use in an atomic fashion.
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uint32_t irq_state = disable_irq();
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uint32_t old_enable_mask = dma_enable_mask;
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dma_enable_mask |= (1 << dma_id);
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enable_irq(irq_state);
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if (dma_id < NSTREAMS_PER_CONTROLLER) {
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if (((old_enable_mask & DMA1_ENABLE_MASK) == 0) && !DMA1_IS_CLK_ENABLED()) {
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__HAL_RCC_DMA1_CLK_ENABLE();
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// We just turned on the clock. This means that anything stored
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// in dma_last_channel (for DMA1) needs to be invalidated.
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for (int channel = 0; channel < NSTREAMS_PER_CONTROLLER; channel++) {
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dma_last_sub_instance[channel] = DMA_INVALID_CHANNEL;
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}
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}
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}
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#if defined(DMA2)
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else {
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if (((old_enable_mask & DMA2_ENABLE_MASK) == 0) && !DMA2_IS_CLK_ENABLED()) {
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__HAL_RCC_DMA2_CLK_ENABLE();
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// We just turned on the clock. This means that anything stored
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// in dma_last_channel (for DMA2) needs to be invalidated.
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for (int channel = NSTREAMS_PER_CONTROLLER; channel < NSTREAM; channel++) {
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dma_last_sub_instance[channel] = DMA_INVALID_CHANNEL;
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}
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}
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}
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#endif
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}
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static void dma_disable_clock(dma_id_t dma_id) {
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// We just mark the clock as disabled here, but we don't actually disable it.
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// We wait for the timer to expire first, which means that back-to-back
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// transfers don't have to initialize as much.
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dma_tickle(dma_id);
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dma_enable_mask &= ~(1 << dma_id);
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}
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void dma_init_handle(DMA_HandleTypeDef *dma, const dma_descr_t *dma_descr, uint32_t dir, void *data) {
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// initialise parameters
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dma->Instance = dma_descr->instance;
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dma->Init = *dma_descr->init;
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dma->Init.Direction = dir;
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dma->Init.Channel = dma_descr->sub_instance;
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// half of __HAL_LINKDMA(data, xxx, *dma)
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// caller must implement other half by doing: data->xxx = dma
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dma->Parent = data;
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}
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void dma_init(DMA_HandleTypeDef *dma, const dma_descr_t *dma_descr, uint32_t dir, void *data){
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// Some drivers allocate the DMA_HandleTypeDef from the stack
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// (i.e. dac, i2c, spi) and for those cases we need to clear the
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// structure so we don't get random values from the stack)
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memset(dma, 0, sizeof(*dma));
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if (dma_descr != NULL) {
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dma_id_t dma_id = dma_descr->id;
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dma_init_handle(dma, dma_descr, dir, data);
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// set global pointer for IRQ handler
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dma_handle[dma_id] = dma;
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dma_enable_clock(dma_id);
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// if this stream was previously configured for this channel/request and direction then we
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// can skip most of the initialisation
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uint8_t sub_inst = DMA_SUB_INSTANCE_AS_UINT8(dma_descr->sub_instance) | (dir == DMA_PERIPH_TO_MEMORY) << 7;
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if (dma_last_sub_instance[dma_id] != sub_inst) {
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dma_last_sub_instance[dma_id] = sub_inst;
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// reset and configure DMA peripheral
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// (dma->State is set to HAL_DMA_STATE_RESET by memset above)
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HAL_DMA_DeInit(dma);
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HAL_DMA_Init(dma);
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svc_setpriority(IRQn_NONNEG(dma_irqn[dma_id]), IRQ_PRI_DMA);
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} else {
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// only necessary initialization
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dma->State = HAL_DMA_STATE_READY;
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// calculate DMA base address and bitshift to be used in IRQ handler
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extern uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
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DMA_CalcBaseAndBitshift(dma);
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}
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svc_enableIRQ(dma_irqn[dma_id]);
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}
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}
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void dma_deinit(const dma_descr_t *dma_descr) {
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if (dma_descr != NULL) {
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svc_disableIRQ(dma_irqn[dma_descr->id]);
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dma_handle[dma_descr->id] = NULL;
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dma_disable_clock(dma_descr->id);
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}
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}
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void dma_invalidate_channel(const dma_descr_t *dma_descr) {
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if (dma_descr != NULL) {
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dma_id_t dma_id = dma_descr->id;
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// Only compare the sub-instance, not the direction bit (MSB)
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if ((dma_last_sub_instance[dma_id] & 0x7f) == DMA_SUB_INSTANCE_AS_UINT8(dma_descr->sub_instance) ) {
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dma_last_sub_instance[dma_id] = DMA_INVALID_CHANNEL;
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}
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}
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}
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// Called from the SysTick handler
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// We use LSB of tick to select which controller to process
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static void dma_idle_handler(uint32_t tick) {
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if (!DMA_IDLE_ENABLED() || !DMA_IDLE_TICK(tick)) {
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return;
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}
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static const uint32_t controller_mask[] = {
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DMA1_ENABLE_MASK,
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#if defined(DMA2)
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DMA2_ENABLE_MASK,
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#endif
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};
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{
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int controller = (tick >> DMA_SYSTICK_LOG2) & 1;
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if (dma_idle.counter[controller] == 0) {
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return;
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}
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if (++dma_idle.counter[controller] > DMA_IDLE_TICK_MAX) {
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if ((dma_enable_mask & controller_mask[controller]) == 0) {
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// Nothing is active and we've reached our idle timeout,
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// Now we'll really disable the clock.
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dma_idle.counter[controller] = 0;
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if (controller == 0) {
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__HAL_RCC_DMA1_CLK_DISABLE();
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}
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#if defined(DMA2)
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else {
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__HAL_RCC_DMA2_CLK_DISABLE();
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}
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#endif
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} else {
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// Something is still active, but the counter never got
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// reset, so we'll reset the counter here.
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dma_idle.counter[controller] = 1;
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}
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}
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}
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}
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