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575 lines
18 KiB
575 lines
18 KiB
#ifndef __TREZORHAL_TRUSTZONE__
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#define __TREZORHAL_TRUSTZONE__
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#ifdef BOARDLOADER
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#define CMSE_NS_CALL __attribute((cmse_nonsecure_call))
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#define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
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typedef void CMSE_NS_CALL (*funcptr)(void);
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/* typedef for non-secure callback functions */
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typedef funcptr funcptr_NS;
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#include STM32_HAL_H
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
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*/
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/*
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// <e>Initialize Security Attribution Unit (SAU) CTRL register
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*/
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#define SAU_INIT_CTRL 1
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/*
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// <q> Enable SAU
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// <i> Value for SAU->CTRL register bit ENABLE
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*/
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#define SAU_INIT_CTRL_ENABLE 0
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/*
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// <o> When SAU is disabled
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// <0=> All Memory is Secure
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// <1=> All Memory is Non-Secure
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// <i> Value for SAU->CTRL register bit ALLNS
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// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory
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map configuration.
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*/
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#define SAU_INIT_CTRL_ALLNS 1
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/*
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// </e>
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*/
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/*
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// <h>Initialize Security Attribution Unit (SAU) Address Regions
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// <i>SAU configuration specifies regions to be one of:
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// <i> - Secure and Non-Secure Callable
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// <i> - Non-Secure
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// <i>Note: All memory regions not configured by SAU are Secure
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*/
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#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
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/*
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// <e>Initialize SAU Region 0
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// <i> Setup SAU Region 0 memory attributes
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*/
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#define SAU_INIT_REGION0 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START0 0x0C1FE000 /* start address of SAU region 0 */
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END0 0x0C1FFFFF /* end address of SAU region 0 */
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC0 1
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/*
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// </e>
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*/
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/*
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// <e>Initialize SAU Region 1
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// <i> Setup SAU Region 1 memory attributes
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*/
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#define SAU_INIT_REGION1 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START1 0x08200000 /* start address of SAU region 1 */
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END1 0x083FFFFF /* end address of SAU region 1 */
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC1 0
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/*
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// </e>
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*/
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/*
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// <e>Initialize SAU Region 2
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// <i> Setup SAU Region 2 memory attributes
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*/
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#define SAU_INIT_REGION2 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START2 0x200D0000 /* start address of SAU region 2 */
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END2 0x2026FFFF /* end address of SAU region 2 */
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC2 0
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/*
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// </e>
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*/
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/*
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// <e>Initialize SAU Region 3
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// <i> Setup SAU Region 3 memory attributes
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*/
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#define SAU_INIT_REGION3 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC3 0
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/*
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// </e>
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*/
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/*
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// <e>Initialize SAU Region 4
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// <i> Setup SAU Region 4 memory attributes
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*/
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#define SAU_INIT_REGION4 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END4 0xAFFFFFFF /* end address of SAU region 4 */
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC4 0
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/*
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// </e>
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*/
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/*
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// <e>Initialize SAU Region 5
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// <i> Setup SAU Region 5 memory attributes
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*/
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#define SAU_INIT_REGION5 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC5 0
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/*
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// </e>
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*/
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/*
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// <e>Initialize SAU Region 6
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// <i> Setup SAU Region 6 memory attributes
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*/
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#define SAU_INIT_REGION6 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC6 0
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/*
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// </e>
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*/
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/*
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// <e>Initialize SAU Region 7
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// <i> Setup SAU Region 7 memory attributes
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*/
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#define SAU_INIT_REGION7 0
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/*
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// <o>Start Address <0-0xFFFFFFE0>
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*/
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#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
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/*
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// <o>End Address <0x1F-0xFFFFFFFF>
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*/
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#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
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/*
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// <o>Region is
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// <0=>Non-Secure
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// <1=>Secure, Non-Secure Callable
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*/
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#define SAU_INIT_NSC7 0
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/*
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// </e>
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*/
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/*
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// </h>
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*/
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/*
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// <e>Setup behaviour of Sleep and Exception Handling
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*/
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#define SCB_CSR_AIRCR_INIT 0
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/*
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// <o> Deep Sleep can be enabled by
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// <0=>Secure and Non-Secure state
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// <1=>Secure state only
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// <i> Value for SCB->CSR register bit DEEPSLEEPS
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*/
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#define SCB_CSR_DEEPSLEEPS_VAL 0
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/*
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// <o>System reset request accessible from
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// <0=> Secure and Non-Secure state
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// <1=> Secure state only
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// <i> Value for SCB->AIRCR register bit SYSRESETREQS
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*/
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#define SCB_AIRCR_SYSRESETREQS_VAL 0
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/*
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// <o>Priority of Non-Secure exceptions is
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// <0=> Not altered
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// <1=> Lowered to 0x04-0x07
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// <i> Value for SCB->AIRCR register bit PRIS
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*/
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#define SCB_AIRCR_PRIS_VAL 0
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/*
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// <o>BusFault, HardFault, and NMI target
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// <0=> Secure state
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// <1=> Non-Secure state
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// <i> Value for SCB->AIRCR register bit BFHFNMINS
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*/
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#define SCB_AIRCR_BFHFNMINS_VAL 0
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/*
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// </e>
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*/
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/*
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// <e>Setup behaviour of Floating Point Unit
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*/
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#define TZ_FPU_NS_USAGE 1
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/*
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// <o>Floating Point Unit usage
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// <0=> Secure state only
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// <3=> Secure and Non-Secure state
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// <i> Value for SCB->NSACR register bits CP10, CP11
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*/
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#define SCB_NSACR_CP10_11_VAL 3
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/*
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// <o>Treat floating-point registers as Secure
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// <0=> Disabled
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// <1=> Enabled
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// <i> Value for FPU->FPCCR register bit TS
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*/
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#define FPU_FPCCR_TS_VAL 0
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/*
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// <o>Clear on return (CLRONRET) accessibility
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// <0=> Secure and Non-Secure state
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// <1=> Secure state only
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// <i> Value for FPU->FPCCR register bit CLRONRETS
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*/
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#define FPU_FPCCR_CLRONRETS_VAL 0
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/*
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// <o>Clear floating-point caller saved registers on exception return
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// <0=> Disabled
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// <1=> Enabled
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// <i> Value for FPU->FPCCR register bit CLRONRET
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*/
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#define FPU_FPCCR_CLRONRET_VAL 1
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/*
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// </e>
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*/
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/*
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// <h>Setup Interrupt Target
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*/
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/*
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// <e>Initialize ITNS 0 (Interrupts 0..31)
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*/
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#define NVIC_INIT_ITNS0 1
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/*
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// Interrupts 0..31
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// <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.1> PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.5> RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.6> FLASH_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.7> FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.8> GTZC_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.9> RCC_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.10> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.11> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.12> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.13> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.14> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.15> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.16> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.17> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.18> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.19> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.20> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.21> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.22> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.23> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.24> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.27> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.29> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.30> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.31> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
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*/
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#define NVIC_INIT_ITNS0_VAL 0x00000000
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/*
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// </e>
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*/
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/*
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// <e>Initialize ITNS 1 (Interrupts 32..63)
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*/
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#define NVIC_INIT_ITNS1 1
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/*
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// Interrupts 32..63
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// <o.0> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.1> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.2> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.3> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.4> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.5> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.6> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.7> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.8> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.9> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.10> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.11> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.12> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.13> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.14> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.15> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.16> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.17> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.18> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.19> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.20> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.21> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.22> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.23> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.24> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.25> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.26> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.27> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.28> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.29> USART1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.30> USART2_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.31> USART3_IRQn <0=> Secure state <1=> Non-Secure state
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*/
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#define NVIC_INIT_ITNS1_VAL 0x00000000
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/*
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// </e>
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*/
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/*
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// <e>Initialize ITNS 2 (Interrupts 64..95)
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*/
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#define NVIC_INIT_ITNS2 1
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/*
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// Interrupts 64..95
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// <o.0> UART4_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.1> UART5_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.2> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.3> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.4> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.5> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.6> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.7> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.8> COMP_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.9> OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.10> CRS_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.11> FMC_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.12> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.13> PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.15> SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.16> GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.17> GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state
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// <o.18> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
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|
// <o.19> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.20> GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.21> GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.22> GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.23> GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.24> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.25> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.26> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.27> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.28> TSC_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.30> RNG_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.31> FPU_IRQn <0=> Secure state <1=> Non-Secure state
|
|
*/
|
|
#define NVIC_INIT_ITNS2_VAL 0x00000000
|
|
|
|
/*
|
|
// </e>
|
|
*/
|
|
|
|
/*
|
|
// <e>Initialize ITNS 3 (Interrupts 96..127)
|
|
*/
|
|
#define NVIC_INIT_ITNS3 1
|
|
|
|
/*
|
|
// Interrupts 96..127
|
|
// <o.0> HASH_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.2> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.3> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.4> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.5> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.6> MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.7> MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.8> MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.9> MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.10> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.11> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.14> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.15> DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.16> ADF1_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.17> ADC4_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.18> LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.19> LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.20> LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.21> LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.22> DMA2D_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.23> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.24> OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.25> MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.26> MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.27> CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.28> FMAC_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.30> USART6_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.31> I2C5_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
|
*/
|
|
#define NVIC_INIT_ITNS3_VAL 0x00000000
|
|
|
|
/*
|
|
// </e>
|
|
*/
|
|
|
|
/*
|
|
// <e>Initialize ITNS 4 (Interrupts 109..138)
|
|
*/
|
|
#define NVIC_INIT_ITNS4 1
|
|
|
|
/*
|
|
// Interrupts 96..138
|
|
// <o.0> I2C5_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.1> I2C6_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.2> I2C6_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.3> HSPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.4> GPU2D_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.5> GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.6> GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.7> LTDC_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.8> LTDC_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.9> DSI_IRQn <0=> Secure state <1=> Non-Secure state
|
|
// <o.10> DCACHE2_IRQn <0=> Secure state <1=> Non-Secure state
|
|
*/
|
|
#define NVIC_INIT_ITNS4_VAL 0x00000000
|
|
|
|
/*
|
|
// </e>
|
|
*/
|
|
|
|
/*
|
|
// </h>
|
|
*/
|
|
|
|
/*
|
|
max 8 SAU regions.
|
|
SAU regions are defined in partition.h
|
|
*/
|
|
|
|
#define SAU_INIT_REGION(n) \
|
|
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
|
|
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
|
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
|
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
|
|
|
extern void trustzone_init(void);
|
|
|
|
extern void trustzone_run(void);
|
|
|
|
#endif
|
|
#endif
|