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232 lines
8.1 KiB
232 lines
8.1 KiB
#include "trustzone.h"
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#ifdef BOARDLOADER
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#include STM32_HAL_H
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void trustzone_init(void) {
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#if defined(__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
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#if defined(SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
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SAU_INIT_REGION(0);
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#endif
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#if defined(SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
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SAU_INIT_REGION(1);
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#endif
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#if defined(SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
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SAU_INIT_REGION(2);
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#endif
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#if defined(SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
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SAU_INIT_REGION(3);
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#endif
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#if defined(SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
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SAU_INIT_REGION(4);
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#endif
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#if defined(SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
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SAU_INIT_REGION(5);
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#endif
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#if defined(SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
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SAU_INIT_REGION(6);
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#endif
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#if defined(SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
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SAU_INIT_REGION(7);
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#endif
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/* repeat this for all possible SAU regions */
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#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
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#if defined(SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
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SAU->CTRL =
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((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
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((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk);
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#endif
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#if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
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SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) |
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((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) &
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SCB_SCR_SLEEPDEEPS_Msk);
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SCB->AIRCR =
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(SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
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SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) |
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((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
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((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) &
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SCB_AIRCR_SYSRESETREQS_Msk) |
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((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
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((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) &
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SCB_AIRCR_BFHFNMINS_Msk);
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#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
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#if defined(__FPU_USED) && (__FPU_USED == 1U) && defined(TZ_FPU_NS_USAGE) && \
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(TZ_FPU_NS_USAGE == 1U)
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SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
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((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) &
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(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
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FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk |
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FPU_FPCCR_CLRONRET_Msk)) |
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((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) |
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((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) &
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FPU_FPCCR_CLRONRETS_Msk) |
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((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) &
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FPU_FPCCR_CLRONRET_Msk);
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#endif
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#if defined(NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
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NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
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#endif
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#if defined(NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
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NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
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#endif
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#if defined(NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
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NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
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#endif
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#if defined(NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
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NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
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#endif
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#if defined(NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
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NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
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#endif
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}
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void trustzone_run(void) {
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uint32_t index;
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MPCBB_ConfigTypeDef MPCBB_desc;
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/* Enable GTZC peripheral clock */
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__HAL_RCC_GTZC1_CLK_ENABLE();
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__HAL_RCC_GTZC2_CLK_ENABLE();
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// HAL_GPIO_ConfigPinAttributes(GPIOA, 0xFFFF, GPIO_PIN_NSEC);
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// HAL_GPIO_ConfigPinAttributes(GPIOB, 0xFFFF, GPIO_PIN_NSEC);
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// HAL_GPIO_ConfigPinAttributes(GPIOC, 0xFFFF, GPIO_PIN_NSEC);
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// HAL_GPIO_ConfigPinAttributes(GPIOD, 0xFFFF, GPIO_PIN_NSEC);
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// HAL_GPIO_ConfigPinAttributes(GPIOE, 0xFFFF, GPIO_PIN_NSEC);
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// HAL_GPIO_ConfigPinAttributes(GPIOF, 0xFFFF, GPIO_PIN_NSEC);
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// HAL_GPIO_ConfigPinAttributes(GPIOG, 0xFFFF, GPIO_PIN_NSEC);
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// HAL_GPIO_ConfigPinAttributes(GPIOH, 0xFFFF, GPIO_PIN_NSEC);
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/* -------------------------------------------------------------------------*/
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/* Memory isolation configuration */
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/* Initializes the memory that secure application books for non secure */
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/* -------------------------------------------------------------------------*/
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/* -------------------------------------------------------------------------*/
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/* Internal RAM : */
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/* The booking is done through GTZC MPCBB. */
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/* Internal SRAMs are secured by default and configured by block */
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/* of 512 bytes. */
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/* Internal SRAM3 (starting from 0x20040000) will be configured as */
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/* fully non-secure. */
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MPCBB_desc.SecureRWIllegalMode = GTZC_MPCBB_SRWILADIS_DISABLE;
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MPCBB_desc.InvertSecureState = GTZC_MPCBB_INVSECSTATE_NOT_INVERTED;
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MPCBB_desc.AttributeConfig.MPCBB_LockConfig_array[0] =
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0x00000000U; /* Unlocked configuration */
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for (index = 0; index < 52; index++) {
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/* Non-secure blocks */
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MPCBB_desc.AttributeConfig.MPCBB_SecConfig_array[index] = 0x00000000U;
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MPCBB_desc.AttributeConfig.MPCBB_PrivConfig_array[index] = 0x00000000U;
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}
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if (HAL_GTZC_MPCBB_ConfigMem(SRAM1_BASE, &MPCBB_desc) != HAL_OK) {
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/* Initialization Error */
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while (1)
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;
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}
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if (HAL_GTZC_MPCBB_ConfigMem(SRAM2_BASE, &MPCBB_desc) != HAL_OK) {
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/* Initialization Error */
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while (1)
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;
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}
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if (HAL_GTZC_MPCBB_ConfigMem(SRAM3_BASE, &MPCBB_desc) != HAL_OK) {
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/* Initialization Error */
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while (1)
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;
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}
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if (HAL_GTZC_MPCBB_ConfigMem(SRAM4_BASE, &MPCBB_desc) != HAL_OK) {
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/* Initialization Error */
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while (1)
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;
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}
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if (HAL_GTZC_MPCBB_ConfigMem(SRAM5_BASE, &MPCBB_desc) != HAL_OK) {
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/* Initialization Error */
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while (1)
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;
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}
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/* -------------------------------------------------------------------------*/
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/* Internal Flash */
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/* The booking is done in both IDAU/SAU and FLASH interface */
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/* Setup done based on Flash dual-bank mode described with 1 area per bank */
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/* Non-secure Flash memory area starting from 0x08100000 (Bank2) */
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/* Flash memory is secured by default and modified with Option Byte Loading */
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/* Insure SECWM2_PSTRT > SECWM2_PEND in order to have all Bank2 non-secure */
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/* -------------------------------------------------------------------------*/
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/* External OctoSPI memory */
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/* The booking is done in both IDAU/SAU and GTZC MPCWM interface */
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/* Default secure configuration */
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/* Else need to use HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() */
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/* -------------------------------------------------------------------------*/
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/* External NOR/FMC memory */
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/* The booking is done in both IDAU/SAU and GTZC MPCWM interface */
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/* Default secure configuration */
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/* Else need to use HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() */
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/* -------------------------------------------------------------------------*/
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/* External NAND/FMC memory */
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/* The booking is done in both IDAU/SAU and GTZC MPCWM interface */
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/* Default secure configuration */
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/* Else need to use HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() */
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/* -------------------------------------------------------------------------*/
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/* Peripheral isolation configuration */
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/* Initializes the peripherals and features that secure application books */
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/* for secure (RCC, PWR, RTC, EXTI, DMA, OTFDEC, etc..) or leave them to */
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/* non-secure (GPIO (secured by default)) */
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/* -------------------------------------------------------------------------*/
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// /* Clear all illegal access flags in GTZC TZIC */
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// if(HAL_GTZC_TZIC_ClearFlag(GTZC_PERIPH_ALL) != HAL_OK)
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// {
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// /* Initialization Error */
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// while(1);
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// }
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//
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// /* Enable all illegal access interrupts in GTZC TZIC */
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// if(HAL_GTZC_TZIC_EnableIT(GTZC_PERIPH_ALL) != HAL_OK)
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// {
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// /* Initialization Error */
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// while(1);
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// }
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//
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// /* Enable GTZC secure interrupt */
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// HAL_NVIC_SetPriority(GTZC_IRQn, 0, 0); /* Highest priority level */
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// HAL_NVIC_EnableIRQ(GTZC_IRQn);
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}
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#endif
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