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299 lines
9.0 KiB
299 lines
9.0 KiB
/*
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* This file is part of the Trezor project, https://trezor.io/
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*
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* Copyright (c) SatoshiLabs
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include STM32_HAL_H
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#include "lowlevel.h"
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#include "flash.h"
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#include "model.h"
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#pragma GCC optimize( \
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"no-stack-protector") // applies to all functions in this file
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#if PRODUCTION
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#define WANT_RDP_LEVEL (OB_RDP_LEVEL_2)
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#define WANT_WRP_PAGE_START 1
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#define WANT_WRP_PAGE_END 6
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#else
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#define WANT_RDP_LEVEL (OB_RDP_LEVEL_0)
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#endif
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// BOR LEVEL 0: Reset level threshold is around 1.7 V
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#define WANT_BOR_LEVEL (OB_BOR_LEVEL_0)
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#define FLASH_OPTR_VALUE \
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((WANT_RDP_LEVEL << FLASH_OPTR_RDP_Pos) | FLASH_OPTR_nRST_STDBY | \
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FLASH_OPTR_nRST_STOP | FLASH_OPTR_IWDG_SW | FLASH_OPTR_IWDG_STOP | \
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FLASH_OPTR_IWDG_STDBY | FLASH_OPTR_WWDG_SW | FLASH_OPTR_DUALBANK | \
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FLASH_OPTR_nSWBOOT0 | FLASH_OPTR_nBOOT0 | FLASH_OPTR_PA15_PUPEN | \
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FLASH_OPTR_BKPRAM_ECC | FLASH_OPTR_SRAM3_ECC | FLASH_OPTR_TZEN | \
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FLASH_OPTR_SRAM_RST | WANT_BOR_LEVEL)
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// TODO set values according to MCU variant
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#define FALSH_SECBOOTADD0R_VALUE \
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((BOARDLOADER_START & 0xFFFFFF80) | FLASH_SECBOOTADD0R_BOOT_LOCK | 0x7C)
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#define FLASH_SECWM1R1_VALUE \
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(0 << FLASH_SECWM1R1_SECWM1_PSTRT_Pos | \
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0xff << FLASH_SECWM1R1_SECWM1_PEND_Pos | 0xFF00FF00)
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#define FLASH_SECWM1R2_VALUE \
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(1 << FLASH_SECWM1R2_HDP1_PEND_Pos | FLASH_SECWM1R2_HDP1EN | 0x7F007F00)
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#define FLASH_SECWM2R1_VALUE \
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(0 << FLASH_SECWM1R1_SECWM1_PSTRT_Pos | \
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0xff << FLASH_SECWM1R1_SECWM1_PEND_Pos | 0xFF00FF00)
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#define FLASH_SECWM2R2_VALUE (0x7F007F00)
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secbool flash_check_option_bytes(void) {
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flash_wait_and_clear_status_flags();
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// check values stored in flash interface registers
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if (FLASH->OPTR !=
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FLASH_OPTR_VALUE) { // ignore bits 0 and 1 because they are control bits
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return secfalse;
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}
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if (FLASH->SECBOOTADD0R != FALSH_SECBOOTADD0R_VALUE) {
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return secfalse;
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}
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#if PRODUCTION
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if (FLASH->WRP1AR != (WANT_WRP_PAGE_START | (WANT_WRP_PAGE_END << 16))) {
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return secfalse;
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}
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#else
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// TODO set values according to MCU variant
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if (FLASH->WRP1AR != 0xFF00FFFF) {
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return secfalse;
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}
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#endif
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// TODO set values according to MCU variant
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if (FLASH->WRP1BR != 0xFF00FFFF) {
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return secfalse;
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}
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// TODO set values according to MCU variant
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if (FLASH->WRP2AR != 0xFF00FFFF) {
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return secfalse;
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}
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// TODO set values according to MCU variant
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if (FLASH->WRP2BR != 0xFF00FFFF) {
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return secfalse;
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}
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return sectrue;
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}
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void flash_lock_option_bytes(void) {
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FLASH->NSCR |= FLASH_NSCR_OPTLOCK; // lock the option bytes
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}
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void flash_unlock_option_bytes(void) {
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if ((FLASH->NSCR & FLASH_NSCR_OPTLOCK) == 0) {
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return; // already unlocked
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}
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// reference RM0090 section 3.7.2
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// write the special sequence to unlock
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FLASH->OPTKEYR = FLASH_OPTKEY1;
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FLASH->OPTKEYR = FLASH_OPTKEY2;
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while (FLASH->NSCR & FLASH_NSCR_OPTLOCK)
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; // wait until the flash option control register is unlocked
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}
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uint32_t flash_set_option_bytes(void) {
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if (flash_unlock_write() != sectrue) {
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return 0;
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}
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flash_wait_and_clear_status_flags();
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flash_unlock_option_bytes();
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flash_wait_and_clear_status_flags();
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FLASH->OPTR =
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FLASH_OPTR_VALUE; // WARNING: dev board safe unless you compile for
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// PRODUCTION or change this value!!!
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FLASH->SECBOOTADD0R = FALSH_SECBOOTADD0R_VALUE;
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#if PRODUCTION
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FLASH->WRP1AR = WANT_WRP_PAGE_START | (WANT_WRP_PAGE_END << 16);
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// TODO set values according to MCU variant
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FLASH->WRP1BR = 0xFF00FFFF;
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FLASH->WRP2AR = 0xFF00FFFF FLASH->WRP2BR = 0xFF00FFFF
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#endif
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FLASH_WaitForLastOperation(HAL_MAX_DELAY);
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FLASH->NSCR |= FLASH_NSCR_OPTSTRT;
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uint32_t result =
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flash_wait_and_clear_status_flags(); // wait until changes are committed
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FLASH_WaitForLastOperation(HAL_MAX_DELAY);
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FLASH->NSCR |= FLASH_NSCR_OBL_LAUNCH; // begin committing changes to flash
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result =
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flash_wait_and_clear_status_flags(); // wait until changes are committed
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flash_lock_option_bytes();
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if (flash_lock_write() != sectrue) {
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return 0;
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}
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return result;
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}
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secbool flash_configure_option_bytes(void) {
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if (sectrue == flash_check_option_bytes()) {
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return sectrue; // we DID NOT have to change the option bytes
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}
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do {
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flash_set_option_bytes();
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} while (sectrue != flash_check_option_bytes());
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return secfalse; // notify that we DID have to change the option bytes
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}
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secbool flash_check_sec_area_ob(void) {
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flash_wait_and_clear_status_flags();
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// check values stored in flash interface registers
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if (FLASH->SECWM1R1 != FLASH_SECWM1R1_VALUE) {
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return secfalse;
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}
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if (FLASH->SECWM1R2 != FLASH_SECWM1R2_VALUE) {
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return secfalse;
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}
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if (FLASH->SECWM2R1 != FLASH_SECWM2R1_VALUE) {
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return secfalse;
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}
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if (FLASH->SECWM2R2 != FLASH_SECWM2R2_VALUE) {
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return secfalse;
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}
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return sectrue;
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}
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uint32_t flash_set_sec_area_ob(void) {
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if (flash_unlock_write() != sectrue) {
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return 0;
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}
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flash_wait_and_clear_status_flags();
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flash_unlock_option_bytes();
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flash_wait_and_clear_status_flags();
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FLASH->SECWM1R1 = FLASH_SECWM1R1_VALUE;
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FLASH->SECWM1R2 = FLASH_SECWM1R2_VALUE;
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FLASH->SECWM2R1 = FLASH_SECWM2R1_VALUE;
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FLASH->SECWM2R2 = FLASH_SECWM2R2_VALUE;
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FLASH_WaitForLastOperation(HAL_MAX_DELAY);
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FLASH->NSCR |= FLASH_NSCR_OPTSTRT;
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uint32_t result =
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flash_wait_and_clear_status_flags(); // wait until changes are committed
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FLASH_WaitForLastOperation(HAL_MAX_DELAY);
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FLASH->NSCR |= FLASH_NSCR_OBL_LAUNCH; // begin committing changes to flash
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result =
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flash_wait_and_clear_status_flags(); // wait until changes are committed
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flash_lock_option_bytes();
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if (flash_lock_write() != sectrue) {
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return 0;
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}
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return result;
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}
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secbool flash_configure_sec_area_ob(void) {
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if (sectrue == flash_check_sec_area_ob()) {
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return sectrue; // we DID NOT have to change the option bytes
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}
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do {
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flash_set_sec_area_ob();
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} while (sectrue != flash_check_sec_area_ob());
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return secfalse; // notify that we DID have to change the option bytes
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}
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void periph_init(void) {
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// STM32U5xx HAL library initialization:
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// - configure the Flash prefetch, instruction and data caches
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// - configure the Systick to generate an interrupt each 1 msec
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// - set NVIC Group Priority to 4
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// - global MSP (MCU Support Package) initialization
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HAL_Init();
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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/** Initializes the common periph clock
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*/
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI;
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PeriphClkInit.DsiClockSelection = RCC_DSICLKSOURCE_PLL3;
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PeriphClkInit.LtdcClockSelection = RCC_LTDCCLKSOURCE_PLL3;
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PeriphClkInit.PLL3.PLL3Source = RCC_PLLSOURCE_HSE;
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PeriphClkInit.PLL3.PLL3M = 4;
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PeriphClkInit.PLL3.PLL3N = 125;
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PeriphClkInit.PLL3.PLL3P = 8;
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PeriphClkInit.PLL3.PLL3Q = 2;
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PeriphClkInit.PLL3.PLL3R = 24;
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PeriphClkInit.PLL3.PLL3RGE = RCC_PLLVCIRANGE_0;
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PeriphClkInit.PLL3.PLL3FRACN = 0;
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PeriphClkInit.PLL3.PLL3ClockOut = RCC_PLL3_DIVP | RCC_PLL3_DIVR;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
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/** Enable instruction cache in 1-way (direct mapped cache)
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*/
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HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
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// Enable GPIO clocks
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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// enable the PVD (programmable voltage detector).
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// select the "2.8V" threshold (level 5).
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// this detector will be active regardless of the
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// flash option byte BOR setting.
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// __HAL_RCC_PWR_CLK_ENABLE();
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// PWR_PVDTypeDef pvd_config;
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// pvd_config.PVDLevel = PWR_PVDLEVEL_5;
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// pvd_config.Mode = PWR_PVD_MODE_IT_RISING_FALLING;
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// HAL_PWR_ConfigPVD(&pvd_config);
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// HAL_PWR_EnablePVD();
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// NVIC_EnableIRQ(PVD_PVM_IRQn);
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}
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secbool reset_flags_check(void) {
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#if PRODUCTION
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// this is effective enough that it makes development painful, so only use it
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// for production. check the reset flags to assure that we arrive here due to
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// a regular full power-on event, and not as a result of a lesser reset.
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if ((RCC->CSR & (RCC_CSR_LPWRRSTF | RCC_CSR_WWDGRSTF | RCC_CSR_IWDGRSTF |
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RCC_CSR_SFTRSTF | RCC_CSR_PINRSTF | RCC_CSR_BORRSTF |
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RCC_CSR_OBLRSTF)) != (RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)) {
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return secfalse;
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}
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#endif
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return sectrue;
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}
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void reset_flags_reset(void) {
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RCC->CSR |= RCC_CSR_RMVF; // clear the reset flags
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}
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