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231 lines
6.5 KiB
231 lines
6.5 KiB
/*
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* This file is part of the Trezor project, https://trezor.io/
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*
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* Copyright (c) SatoshiLabs
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include STM32_HAL_H
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#include "platform.h"
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#include "rng.h"
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#include TREZOR_BOARD
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const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U,
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1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
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const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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const uint32_t MSIRangeTable[16] = {48000000U, 24000000U, 16000000U, 12000000U,
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4000000U, 2000000U, 1330000U, 1000000U,
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3072000U, 1536000U, 1024000U, 768000U,
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400000U, 200000U, 133000U, 100000U};
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typedef struct {
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uint32_t freq;
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uint32_t pllq;
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uint32_t pllp;
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uint32_t pllm;
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uint32_t plln;
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} clock_conf_t;
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#if defined STM32U5
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#define DEFAULT_FREQ 160U
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#define DEFAULT_PLLM 1
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#define DEFAULT_PLLN (10 * PLLN_COEF) // mult by 10
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#define DEFAULT_PLLR 1U // division by 1
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#define DEFAULT_PLLQ 1U // division by 1
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#define DEFAULT_PLLP 5U // division by 5
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#else
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#error Unsupported MCU
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#endif
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uint32_t SystemCoreClock = DEFAULT_FREQ * 1000000U;
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// PLLCLK = ((HSE / PLLM) * PLLN) / PLLR
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#ifdef HSE_16MHZ
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#define PLLN_COEF 1U
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#elif defined HSE_8MHZ
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#define PLLN_COEF 2U
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#else
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// no HSE available, use 16MHz HSI
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#define HSI_ONLY
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#define PLLN_COEF 1U
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#endif
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// assuming HSE 16 MHz
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clock_conf_t clock_conf[1] = {
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{
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// clk = ((16MHz / 1) * 10) / 1 = 160 MHz
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.freq = 160,
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.pllp = 1,
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.pllq = 1,
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.pllm = 1,
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.plln = 10 * PLLN_COEF,
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},
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};
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#pragma GCC optimize( \
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"no-stack-protector") // applies to all functions in this file
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void SystemInit(void) {
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// set flash wait states for an increasing HCLK frequency
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FLASH->ACR = FLASH_ACR_LATENCY_5WS;
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// wait until the new wait state config takes effect -- per section 3.5.1
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// guidance
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while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_ACR_LATENCY_5WS)
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;
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set MSION bit */
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RCC->CR = RCC_CR_MSISON;
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/* Reset CFGR register */
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RCC->CFGR1 = 0U;
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RCC->CFGR2 = 0U;
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RCC->CFGR3 = 0U;
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/* Reset HSEON, CSSON , HSION, PLLxON bits */
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RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON |
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RCC_CR_PLL3ON | RCC_CR_HSI48ON);
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/* Reset PLLCFGR register */
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RCC->PLL1CFGR = 0U;
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/* Reset HSEBYP bit */
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RCC->CR &= ~(RCC_CR_HSEBYP);
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/* Disable all interrupts */
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RCC->CIER = 0U;
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__HAL_RCC_PWR_CLK_ENABLE();
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MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN),
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PWR_REGULATOR_VOLTAGE_SCALE1);
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while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY))
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;
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while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY))
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;
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#ifndef HSI_ONLY
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__HAL_RCC_HSE_CONFIG(RCC_HSE_ON);
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while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
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;
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__HAL_RCC_PLL_CONFIG(RCC_PLLSOURCE_HSE, RCC_PLLMBOOST_DIV1, DEFAULT_PLLM,
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DEFAULT_PLLN, DEFAULT_PLLP, DEFAULT_PLLQ, DEFAULT_PLLR);
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#else
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RCC->CR |= RCC_CR_HSION;
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// wait until the HSI is on
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while ((RCC->CR & RCC_CR_HSION) != RCC_CR_HSION)
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;
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__HAL_RCC_PLL_CONFIG(RCC_PLLSOURCE_HSI, RCC_PLLMBOOST_DIV1, DEFAULT_PLLM,
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DEFAULT_PLLN, DEFAULT_PLLP, DEFAULT_PLLQ, DEFAULT_PLLR);
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#endif
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__HAL_RCC_PLL_FRACN_DISABLE();
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__HAL_RCC_PLL_VCIRANGE(RCC_PLLVCIRANGE_1);
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__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
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__HAL_RCC_PLL_ENABLE();
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while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U)
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;
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__HAL_RCC_HSI48_ENABLE();
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while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U)
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;
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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FLASH->ACR = FLASH_ACR_LATENCY_4WS;
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// wait until the new wait state config takes effect -- per section 3.5.1
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// guidance
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while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_ACR_LATENCY_4WS)
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;
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MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, RCC_HCLK_DIV1);
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MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((RCC_HCLK_DIV1) << 4));
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MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, RCC_HCLK_DIV1);
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MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, RCC_SYSCLK_DIV1);
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MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, RCC_SYSCLKSOURCE_PLLCLK);
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/*
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* Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
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*/
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HAL_PWREx_DisableUCPDDeadBattery();
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#ifdef USE_SMPS
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/*
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* Switch to SMPS regulator instead of LDO
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*/
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SET_BIT(PWR->CR3, PWR_CR3_REGSEL);
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/* Wait until system switch on new regulator */
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while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS))
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;
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#endif
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// enable power supply for GPIOG 2 to 15
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PWR->SVMCR |= PWR_SVMCR_IO2SV;
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__HAL_RCC_PWR_CLK_DISABLE();
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// this will be overriden by static initialization
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SystemCoreClock = DEFAULT_FREQ * 1000000U;
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#ifndef HSI_ONLY
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// enable clock security system
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RCC->CR |= RCC_CR_CSSON;
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// turn off the HSI as it is now unused (it will be turned on again
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// automatically if a clock security failure occurs)
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RCC->CR &= ~RCC_CR_HSION;
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// wait until the HSI is off
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while ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
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;
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#endif
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// TODO turn off MSI?
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// init the TRNG peripheral
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rng_init();
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// set CP10 and CP11 to enable full access to the fpu coprocessor;
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SCB->CPACR |=
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((3UL << 20U) | (3UL << 22U)); /* set CP10 and CP11 Full Access */
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#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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SCB_NS->CPACR |=
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((3UL << 20U) | (3UL << 22U)); /* set CP10 and CP11 Full Access */
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#endif
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// enable instruction cache in default 2-way mode
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ICACHE->CR = ICACHE_CR_EN;
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}
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void drop_privileges(void) {
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// jump to unprivileged mode
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// http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/CHDBIBGJ.html
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__asm__ volatile("msr control, %0" ::"r"(0x1));
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__asm__ volatile("isb");
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}
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// from util.s
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extern void shutdown_privileged(void);
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void PVD_PVM_IRQHandler(void) {
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TIM1->CCR1 = 0; // turn off display backlight
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shutdown_privileged();
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}
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