tychovrahe c3f84e2949 perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256 ... [no changelog]		2024-02-29 23:05:56 +01:00
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vendor_dev_DO_NOT_SIGN.json	perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256	2024-02-29 23:05:56 +01:00
vendor_dev_DO_NOT_SIGN.toif	feat(core): add support for STM32U5A9J-DK board	2024-02-29 23:05:56 +01:00
vendor_unsafe.json	feat(core): add support for STM32U5A9J-DK board	2024-02-29 23:05:56 +01:00
vendor_unsafe.toif	feat(core): add support for STM32U5A9J-DK board	2024-02-29 23:05:56 +01:00
vendorheader_dev_DO_NOT_SIGN_signed_dev.bin	perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256	2024-02-29 23:05:56 +01:00
vendorheader_dev_DO_NOT_SIGN_unsigned.bin	perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256	2024-02-29 23:05:56 +01:00
vendorheader_unsafe_signed_dev.bin	perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256	2024-02-29 23:05:56 +01:00
vendorheader_unsafe_unsigned.bin	feat(core): add support for STM32U5A9J-DK board	2024-02-29 23:05:56 +01:00