mirror of
https://github.com/trezor/trezor-firmware.git
synced 2025-07-02 04:42:33 +00:00
115 lines
3.6 KiB
C
115 lines
3.6 KiB
C
/*
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* This file is part of the Trezor project, https://trezor.io/
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*
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* Copyright (c) SatoshiLabs
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <trustzone.h>
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#include STM32_HAL_H
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#ifdef BOARDLOADER
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// Configure ARMCortex-M33 SCB and FPU security
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static void trustzone_configure_arm(void) {
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// Enable FPU in both secure and non-secure modes
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SCB->NSACR |= SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk;
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// Treat FPU registers as non-secure
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FPU->FPCCR &= ~FPU_FPCCR_TS_Msk;
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// CLRONRET field is accessible from both security states
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FPU->FPCCR &= ~FPU_FPCCR_CLRONRETS_Msk;
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// FPU registers are cleared on exception return
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FPU->FPCCR |= FPU_FPCCR_CLRONRET_Msk;
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}
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// Configure SRAM security
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static void trustzone_configure_sram(void) {
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MPCBB_ConfigTypeDef mpcbb = {0};
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// No exceptions on illegal access
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mpcbb.SecureRWIllegalMode = GTZC_MPCBB_SRWILADIS_DISABLE;
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// Settings of SRAM clock in RCC is secure
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mpcbb.InvertSecureState = GTZC_MPCBB_INVSECSTATE_NOT_INVERTED;
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// Set configuration as unlocked
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mpcbb.AttributeConfig.MPCBB_LockConfig_array[0] = 0x00000000U;
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// Set all blocks secured & unprivileged
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for (int index = 0; index < 52; index++) {
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mpcbb.AttributeConfig.MPCBB_SecConfig_array[index] = 0xFFFFFFFFU;
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mpcbb.AttributeConfig.MPCBB_PrivConfig_array[index] = 0x00000000U;
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}
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HAL_GTZC_MPCBB_ConfigMem(SRAM1_BASE, &mpcbb);
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HAL_GTZC_MPCBB_ConfigMem(SRAM2_BASE, &mpcbb);
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HAL_GTZC_MPCBB_ConfigMem(SRAM3_BASE, &mpcbb);
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HAL_GTZC_MPCBB_ConfigMem(SRAM4_BASE, &mpcbb);
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#if defined STM32U5A9xx | defined STM32U5G9xx
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HAL_GTZC_MPCBB_ConfigMem(SRAM5_BASE, &mpcbb);
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#endif
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#if defined STM32U5G9xx
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HAL_GTZC_MPCBB_ConfigMem(SRAM6_BASE, &mpcbb);
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#endif
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}
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// Configure FLASH security
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static void trustzone_configure_flash(void) {
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FLASH_BBAttributesTypeDef flash_bb = {0};
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// Set all blocks as secured
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for (int index = 0; index < FLASH_BLOCKBASED_NB_REG; index++) {
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flash_bb.BBAttributes_array[index] = 0xFFFFFFFF;
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}
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flash_bb.Bank = FLASH_BANK_1;
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flash_bb.BBAttributesType = FLASH_BB_SEC;
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HAL_FLASHEx_ConfigBBAttributes(&flash_bb);
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flash_bb.Bank = FLASH_BANK_2;
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flash_bb.BBAttributesType = FLASH_BB_SEC;
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HAL_FLASHEx_ConfigBBAttributes(&flash_bb);
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}
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void trustzone_init_boardloader(void) {
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// Configure ARM SCB/FBU security
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trustzone_configure_arm();
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// Enable GTZC (Global Trust-Zone Controller) peripheral clock
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__HAL_RCC_GTZC1_CLK_ENABLE();
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__HAL_RCC_GTZC2_CLK_ENABLE();
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// Configure SRAM security attributes
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trustzone_configure_sram();
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// Configure FLASH security attributes
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trustzone_configure_flash();
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// Make all peripherals secure
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HAL_GTZC_TZSC_ConfigPeriphAttributes(GTZC_PERIPH_ALL, GTZC_TZSC_PERIPH_SEC);
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// Clear all illegal access flags in GTZC TZIC
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HAL_GTZC_TZIC_ClearFlag(GTZC_PERIPH_ALL);
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// Enable all illegal access interrupts in GTZC TZIC
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HAL_GTZC_TZIC_EnableIT(GTZC_PERIPH_ALL);
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// Enable GTZC secure interrupt
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HAL_NVIC_SetPriority(GTZC_IRQn, 0, 0); // Highest priority level
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HAL_NVIC_EnableIRQ(GTZC_IRQn);
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}
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#endif // BOARDLOADER
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