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446 lines
14 KiB
446 lines
14 KiB
/**
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******************************************************************************
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* @file stm32f429i_discovery_sdram.c
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* @author MCD Application Team
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* @brief This file provides a set of functions needed to drive the
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* IS42S16400J SDRAM memory mounted on STM32F429I-Discovery Kit.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "sdram.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup STM32F429I_DISCOVERY
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* @{
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM STM32F429I DISCOVERY SDRAM
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* @{
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Types_Definitions STM32F429I
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* DISCOVERY SDRAM Private Types Definitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Defines STM32F429I DISCOVERY
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* SDRAM Private Defines
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Macros STM32F429I DISCOVERY
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* SDRAM Private Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Variables STM32F429I DISCOVERY
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* SDRAM Private Variables
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* @{
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*/
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static SDRAM_HandleTypeDef SdramHandle;
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static FMC_SDRAM_TimingTypeDef Timing;
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static FMC_SDRAM_CommandTypeDef Command;
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void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
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/**
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* @}
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Function_Prototypes STM32F429I
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* DISCOVERY SDRAM Private Function Prototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Functions STM32F429I DISCOVERY
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* SDRAM Private Functions
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* @{
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*/
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/**
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* @brief Initializes the SDRAM device.
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*/
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void sdram_init(void) {
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static uint8_t sdramstatus = SDRAM_ERROR;
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/* SDRAM device configuration */
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SdramHandle.Instance = FMC_SDRAM_DEVICE;
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/* FMC Configuration -------------------------------------------------------*/
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/* FMC SDRAM Bank configuration */
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/* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */
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/* TMRD: 2 Clock cycles */
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Timing.LoadToActiveDelay = 2;
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/* TXSR: min=70ns (7x11.11ns) */
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Timing.ExitSelfRefreshDelay = 7;
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/* TRAS: min=42ns (4x11.11ns) max=120k (ns) */
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Timing.SelfRefreshTime = 4;
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/* TRC: min=70 (7x11.11ns) */
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Timing.RowCycleDelay = 7;
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/* TWR: min=1+ 7ns (1+1x11.11ns) */
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Timing.WriteRecoveryTime = 2;
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/* TRP: 20ns => 2x11.11ns*/
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Timing.RPDelay = 2;
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/* TRCD: 20ns => 2x11.11ns */
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Timing.RCDDelay = 2;
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/* FMC SDRAM control configuration */
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SdramHandle.Init.SDBank = FMC_SDRAM_BANK2;
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/* Row addressing: [7:0] */
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SdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
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/* Column addressing: [11:0] */
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SdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
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SdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
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SdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
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SdramHandle.Init.CASLatency = SDRAM_CAS_LATENCY;
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SdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
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SdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
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SdramHandle.Init.ReadBurst = SDRAM_READBURST;
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SdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
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/* SDRAM controller initialization */
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/* __weak function can be surcharged by the application code */
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BSP_SDRAM_MspInit(&SdramHandle, (void *)NULL);
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if (HAL_SDRAM_Init(&SdramHandle, &Timing) != HAL_OK) {
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sdramstatus = SDRAM_ERROR;
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} else {
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sdramstatus = SDRAM_OK;
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}
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/* SDRAM initialization sequence */
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BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
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(void)sdramstatus;
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}
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/**
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* @brief Programs the SDRAM device.
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* @param RefreshCount: SDRAM refresh counter value
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*/
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void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) {
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__IO uint32_t tmpmrd = 0;
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/* Step 1: Configure a clock configuration enable command */
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Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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Command.AutoRefreshNumber = 1;
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Command.ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(&SdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 2: Insert 100 us minimum delay */
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/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
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HAL_Delay(1);
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/* Step 3: Configure a PALL (precharge all) command */
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Command.CommandMode = FMC_SDRAM_CMD_PALL;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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Command.AutoRefreshNumber = 1;
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Command.ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(&SdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 4: Configure an Auto Refresh command */
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Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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Command.AutoRefreshNumber = 4;
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Command.ModeRegisterDefinition = 0;
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/* Send the command */
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HAL_SDRAM_SendCommand(&SdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 5: Program the external memory mode register */
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tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | SDRAM_MODEREG_CAS_LATENCY_3 |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
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Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
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Command.AutoRefreshNumber = 1;
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Command.ModeRegisterDefinition = tmpmrd;
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/* Send the command */
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HAL_SDRAM_SendCommand(&SdramHandle, &Command, SDRAM_TIMEOUT);
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/* Step 6: Set the refresh rate counter */
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/* Set the device refresh rate */
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HAL_SDRAM_ProgramRefreshRate(&SdramHandle, RefreshCount);
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}
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/**
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* @brief Reads an mount of data from the SDRAM memory in polling mode.
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* @param uwStartAddress : Read start address
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* @param pData : Pointer to data to be read
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* @param uwDataSize: Size of read data from the memory
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*/
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uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData,
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uint32_t uwDataSize) {
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if (HAL_SDRAM_Read_32b(&SdramHandle, (uint32_t *)uwStartAddress, pData,
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uwDataSize) != HAL_OK) {
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return SDRAM_ERROR;
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} else {
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return SDRAM_OK;
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}
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}
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/**
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* @brief Reads an mount of data from the SDRAM memory in DMA mode.
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* @param uwStartAddress : Read start address
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* @param pData : Pointer to data to be read
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* @param uwDataSize: Size of read data from the memory
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*/
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uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData,
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uint32_t uwDataSize) {
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if (HAL_SDRAM_Read_DMA(&SdramHandle, (uint32_t *)uwStartAddress, pData,
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uwDataSize) != HAL_OK) {
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return SDRAM_ERROR;
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} else {
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return SDRAM_OK;
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}
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}
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/**
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* @brief Writes an mount of data to the SDRAM memory in polling mode.
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* @param uwStartAddress : Write start address
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* @param pData : Pointer to data to be written
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* @param uwDataSize: Size of written data from the memory
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*/
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uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData,
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uint32_t uwDataSize) {
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/* Disable write protection */
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HAL_SDRAM_WriteProtection_Disable(&SdramHandle);
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/*Write 32-bit data buffer to SDRAM memory*/
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if (HAL_SDRAM_Write_32b(&SdramHandle, (uint32_t *)uwStartAddress, pData,
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uwDataSize) != HAL_OK) {
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return SDRAM_ERROR;
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} else {
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return SDRAM_OK;
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}
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}
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/**
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* @brief Writes an mount of data to the SDRAM memory in DMA mode.
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* @param uwStartAddress : Write start address
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* @param pData : Pointer to data to be written
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* @param uwDataSize: Size of written data from the memory
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*/
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uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData,
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uint32_t uwDataSize) {
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if (HAL_SDRAM_Write_DMA(&SdramHandle, (uint32_t *)uwStartAddress, pData,
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uwDataSize) != HAL_OK) {
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return SDRAM_ERROR;
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} else {
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return SDRAM_OK;
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}
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}
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/**
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* @brief Sends command to the SDRAM bank.
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* @param SdramCmd: Pointer to SDRAM command structure
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* @retval HAL status
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*/
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uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) {
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if (HAL_SDRAM_SendCommand(&SdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) {
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return SDRAM_ERROR;
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} else {
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return SDRAM_OK;
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}
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}
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/**
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* @brief Handles SDRAM DMA transfer interrupt request.
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*/
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void BSP_SDRAM_DMA_IRQHandler(void) { HAL_DMA_IRQHandler(SdramHandle.hdma); }
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/**
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* @brief Initializes SDRAM MSP.
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* @note This function can be surcharged by application code.
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* @param hsdram: pointer on SDRAM handle
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* @param Params: pointer on additional configuration parameters, can be NULL.
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*/
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void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) {
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static DMA_HandleTypeDef dmaHandle;
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GPIO_InitTypeDef GPIO_InitStructure = {0};
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if (hsdram != (SDRAM_HandleTypeDef *)NULL) {
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/* Enable FMC clock */
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__HAL_RCC_FMC_CLK_ENABLE();
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/* Enable chosen DMAx clock */
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__DMAx_CLK_ENABLE();
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/* Enable GPIOs clock */
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOF_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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/*-- GPIOs Configuration
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* -----------------------------------------------------*/
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/*
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+-------------------+--------------------+--------------------+--------------------+
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+ SDRAM pins assignment +
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+-------------------+--------------------+--------------------+--------------------+
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| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <->
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FMC_A10 | | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 |
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PG1 <-> FMC_A11 | | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <->
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FMC_A2 | PG8 <-> FMC_SDCLK | | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 |
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PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | | PD10 <-> FMC_D15 | PE9 <->
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FMC_D6 | PF4 <-> FMC_A4 |--------------------+ | PD14 <-> FMC_D0 |
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PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | | PD15 <-> FMC_D1 | PE11 <->
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FMC_D8 | PF11 <-> FMC_NRAS |
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+-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 |
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| PE13 <-> FMC_D10 | PF13 <-> FMC_A7 |
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| PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
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| PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
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+-------------------+--------------------+--------------------+
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| PB5 <-> FMC_SDCKE1|
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| PB6 <-> FMC_SDNE1 |
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| PC0 <-> FMC_SDNWE |
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+-------------------+
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*/
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/* Common GPIO configuration */
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GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStructure.Speed = GPIO_SPEED_FAST;
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GPIO_InitStructure.Pull = GPIO_NOPULL;
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GPIO_InitStructure.Alternate = GPIO_AF12_FMC;
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/* GPIOB configuration */
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GPIO_InitStructure.Pin = GPIO_PIN_5 | GPIO_PIN_6;
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HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
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/* GPIOC configuration */
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GPIO_InitStructure.Pin = GPIO_PIN_0;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
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/* GPIOD configuration */
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GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
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GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOD, &GPIO_InitStructure);
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/* GPIOE configuration */
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GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 |
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 |
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GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOE, &GPIO_InitStructure);
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/* GPIOF configuration */
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GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 |
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GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_11 |
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GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOF, &GPIO_InitStructure);
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/* GPIOG configuration */
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GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 |
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GPIO_PIN_8 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
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/* Configure common DMA parameters */
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dmaHandle.Init.Channel = SDRAM_DMAx_CHANNEL;
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dmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY;
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dmaHandle.Init.PeriphInc = DMA_PINC_ENABLE;
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dmaHandle.Init.MemInc = DMA_MINC_ENABLE;
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dmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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dmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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dmaHandle.Init.Mode = DMA_NORMAL;
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dmaHandle.Init.Priority = DMA_PRIORITY_HIGH;
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dmaHandle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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dmaHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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dmaHandle.Init.MemBurst = DMA_MBURST_SINGLE;
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dmaHandle.Init.PeriphBurst = DMA_PBURST_SINGLE;
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dmaHandle.Instance = SDRAM_DMAx_STREAM;
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/* Associate the DMA handle */
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__HAL_LINKDMA(hsdram, hdma, dmaHandle);
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/* Deinitialize the stream for new transfer */
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HAL_DMA_DeInit(&dmaHandle);
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/* Configure the DMA stream */
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HAL_DMA_Init(&dmaHandle);
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/* NVIC configuration for DMA transfer complete interrupt */
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HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0);
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HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
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} /* of if(hsdram != (SDRAM_HandleTypeDef *)NULL) */
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}
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/**
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* @brief DeInitializes SDRAM MSP.
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* @note This function can be surcharged by application code.
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* @param hsdram: pointer on SDRAM handle
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* @param Params: pointer on additional configuration parameters, can be NULL.
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*/
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void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) {
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static DMA_HandleTypeDef dma_handle;
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if (hsdram != (SDRAM_HandleTypeDef *)NULL) {
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/* Disable NVIC configuration for DMA interrupt */
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HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
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/* Deinitialize the stream for new transfer */
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dma_handle.Instance = SDRAM_DMAx_STREAM;
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HAL_DMA_DeInit(&dma_handle);
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/* DeInit GPIO pins can be done in the application
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(by surcharging this __weak function) */
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/* GPIO pins clock, FMC clock and DMA clock can be shut down in the
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application by surcharging this __weak function */
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} /* of if(hsdram != (SDRAM_HandleTypeDef *)NULL) */
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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