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https://github.com/trezor/trezor-firmware.git
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5dae02bbbf
According to specs, the display can handle up to 10 MHz SPI traffic (minimum cycle time is 100 ns). This patch sets the SPI port to 7.5 MHz (60 MHz clock with divisor 8). In my tests the display works even fine with SPI frequency at 60 MHz. I also minimized the delays (the spec doesn't require a long setup time) and use the registers to check when transfer is done instead of using a fixed delay. This patch also changes the swipe function to swipe pixel by pixel. Otherwise, the swipe would happen too fast to be seen. This changes the display update time from 11 ms to 1.5 ms.
76 lines
2.6 KiB
C
76 lines
2.6 KiB
C
/*
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* This file is part of the TREZOR project.
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*
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* Copyright (C) 2014 Pavol Rusnak <stick@satoshilabs.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/spi.h>
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#include <libopencm3/stm32/f2/rng.h>
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void setup(void)
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{
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// setup clock
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struct rcc_clock_scale clock = rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_120MHZ];
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rcc_clock_setup_hse_3v3(&clock);
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// enable GPIO clock - A (oled), B(oled), C (buttons)
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rcc_periph_clock_enable(RCC_GPIOA);
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rcc_periph_clock_enable(RCC_GPIOB);
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rcc_periph_clock_enable(RCC_GPIOC);
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// enable SPI clock
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rcc_periph_clock_enable(RCC_SPI1);
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// enable OTG FS clock
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rcc_periph_clock_enable(RCC_OTGFS);
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// enable RNG
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rcc_periph_clock_enable(RCC_RNG);
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RNG_CR |= RNG_CR_IE | RNG_CR_RNGEN;
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// set GPIO for buttons
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gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, GPIO2 | GPIO5);
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// set GPIO for OLED display
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gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO4);
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gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0 | GPIO1);
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// enable SPI 1 for OLED display
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO7);
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gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO7);
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// spi_disable_crc(SPI1);
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spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
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spi_enable_ss_output(SPI1);
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// spi_enable_software_slave_management(SPI1);
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// spi_set_nss_high(SPI1);
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// spi_clear_mode_fault(SPI1);
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spi_enable(SPI1);
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// enable OTG_FS
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11 | GPIO12);
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gpio_set_af(GPIOA, GPIO_AF10, GPIO11 | GPIO12);
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}
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void setupApp(void)
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{
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// hotfix for old bootloader
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gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO9);
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spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
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}
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