mirror of
https://github.com/trezor/trezor-firmware.git
synced 2024-12-23 06:48:16 +00:00
124 lines
4.6 KiB
C
124 lines
4.6 KiB
C
/*
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* This file is part of the TREZOR project.
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*
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* Copyright (C) 2014 Pavol Rusnak <stick@satoshilabs.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/cm3/scb.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/spi.h>
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#include <libopencm3/stm32/f2/rng.h>
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#include "rng.h"
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#include "layout.h"
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uint32_t __stack_chk_guard;
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void __attribute__((noreturn)) __stack_chk_fail(void)
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{
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layoutDialog(&bmp_icon_error, NULL, NULL, NULL, "Stack smashing", "detected.", NULL, "Please unplug", "the device.", NULL);
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for (;;) {} // loop forever
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}
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void nmi_handler(void)
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{
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// Clock Security System triggered NMI
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if ((RCC_CIR & RCC_CIR_CSSF) != 0) {
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layoutDialog(&bmp_icon_error, NULL, NULL, NULL, "Clock instability", "detected.", NULL, "Please unplug", "the device.", NULL);
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for (;;) {} // loop forever
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}
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}
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void setup(void)
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{
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// set SCB_CCR STKALIGN bit to make sure 8-byte stack alignment on exception entry is in effect.
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// This is not strictly necessary for the current TREZOR system.
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// This is here to comply with guidance from section 3.3.3 "Binary compatibility with other Cortex processors"
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// of the ARM Cortex-M3 Processor Technical Reference Manual.
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// According to section 4.4.2 and 4.4.7 of the "STM32F10xxx/20xxx/21xxx/L1xxxx Cortex-M3 programming manual",
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// STM32F2 series MCUs are r2p0 and always have this bit set on reset already.
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SCB_CCR |= SCB_CCR_STKALIGN;
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// setup clock
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struct rcc_clock_scale clock = rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_120MHZ];
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rcc_clock_setup_hse_3v3(&clock);
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// enable GPIO clock - A (oled), B(oled), C (buttons)
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rcc_periph_clock_enable(RCC_GPIOA);
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rcc_periph_clock_enable(RCC_GPIOB);
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rcc_periph_clock_enable(RCC_GPIOC);
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// enable SPI clock
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rcc_periph_clock_enable(RCC_SPI1);
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// enable OTG FS clock
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rcc_periph_clock_enable(RCC_OTGFS);
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// enable RNG
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rcc_periph_clock_enable(RCC_RNG);
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RNG_CR |= RNG_CR_RNGEN;
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// to be extra careful and heed the STM32F205xx Reference manual, Section 20.3.1
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// we don't use the first random number generated after setting the RNGEN bit in setup
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random32();
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// enable CSS (Clock Security System)
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RCC_CR |= RCC_CR_CSSON;
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// set GPIO for buttons
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gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, GPIO2 | GPIO5);
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// set GPIO for OLED display
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gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO4);
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gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0 | GPIO1);
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// enable SPI 1 for OLED display
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO7);
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gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO7);
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// spi_disable_crc(SPI1);
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spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
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spi_enable_ss_output(SPI1);
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// spi_enable_software_slave_management(SPI1);
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// spi_set_nss_high(SPI1);
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// spi_clear_mode_fault(SPI1);
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spi_enable(SPI1);
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// enable OTG_FS
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gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11 | GPIO12);
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gpio_set_af(GPIOA, GPIO_AF10, GPIO11 | GPIO12);
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}
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void setupApp(void)
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{
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// for completeness, disable RNG peripheral interrupts for old bootloaders that had
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// enabled them in RNG control register (the RNG interrupt was never enabled in the NVIC)
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RNG_CR &= ~RNG_CR_IE;
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// the static variables in random32 are separate between the bootloader and firmware.
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// therefore, they need to be initialized here so that we can be sure to avoid dupes.
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// this is to try to comply with STM32F205xx Reference manual - Section 20.3.1:
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// "Each subsequent generated random number has to be compared with the previously generated
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// number. The test fails if any two compared numbers are equal (continuous random number generator test)."
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random32();
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// enable CSS (Clock Security System)
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RCC_CR |= RCC_CR_CSSON;
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// hotfix for old bootloader
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gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO9);
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spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
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}
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