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212 lines
6.3 KiB
212 lines
6.3 KiB
/*
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* This file is part of the Trezor project, https://trezor.io/
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*
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* Copyright (c) SatoshiLabs
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include STM32_HAL_H
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#include "platform.h"
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#include "rng.h"
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0,
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1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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typedef struct {
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uint32_t freq;
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uint32_t pllq;
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uint32_t pllp;
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uint32_t pllm;
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uint32_t plln;
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} clock_conf_t;
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#if defined STM32F427xx || defined STM32F429xx
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#ifdef TREZOR_MODEL_T
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#define DEFAULT_FREQ 168U
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#define DEFAULT_PLLQ 7U
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#define DEFAULT_PLLP 0U // P = 2 (two bits, 00 means PLLP = 2)
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#define DEFAULT_PLLM 4U
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#define DEFAULT_PLLN 168U
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#else
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#define DEFAULT_FREQ 180U
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#define DEFAULT_PLLQ 15U
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#define DEFAULT_PLLP 1U // P = 4 (two bits, 01 means PLLP = 4)
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#define DEFAULT_PLLM 4U
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#define DEFAULT_PLLN 360U
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#endif
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#elif STM32F405xx
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#define DEFAULT_FREQ 120U
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#define DEFAULT_PLLQ 5U
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#define DEFAULT_PLLP 0U // P = 2 (two bits, 00 means PLLP = 2)
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#define DEFAULT_PLLM 8U
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#define DEFAULT_PLLN 240U
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#else
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#error Unsupported MCU
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#endif
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uint32_t SystemCoreClock = DEFAULT_FREQ * 1000000U;
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// assuming HSE 8 MHz
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clock_conf_t clock_conf[3] = {
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{
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// P = 4 (two bits, 01 means PLLP = 4)
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// clk = ((8MHz / 4) * 360) / 4 = 180 MHz
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// usb = ((8MHz / 4) * 360) / 15 = 48 MHz
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180,
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15,
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1,
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4,
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360,
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},
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{
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// P = 2 (two bits, 00 means PLLP = 2)
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// clk = ((8MHz / 4) * 168) / 2 = 168 MHz
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// usb = ((8MHz / 4) * 168) / 7 = 48 MHz
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168,
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7,
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0,
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4,
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168,
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},
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{
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// P = 2 (two bits, 00 means PLLP = 2)
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// clk = ((8MHz / 8) * 240) / 2 = 120 MHz
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// usb = ((8MHz / 8) * 240) / 5 = 48 MHz
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120,
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5,
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0,
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8,
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240,
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},
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};
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#pragma GCC optimize( \
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"no-stack-protector") // applies to all functions in this file
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void SystemInit(void) {
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// set flash wait states for an increasing HCLK frequency -- reference RM0090
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// section 3.5.1
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FLASH->ACR = FLASH_ACR_LATENCY_5WS;
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// wait until the new wait state config takes effect -- per section 3.5.1
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// guidance
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while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLASH_ACR_LATENCY_5WS)
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;
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// configure main PLL
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// reference RM0090 section 6.3.2
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RCC->PLLCFGR =
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(RCC_PLLCFGR_RST_VALUE & ~RCC_PLLCFGR_PLLQ & ~RCC_PLLCFGR_PLLSRC &
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~RCC_PLLCFGR_PLLP & ~RCC_PLLCFGR_PLLN & ~RCC_PLLCFGR_PLLM) |
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(DEFAULT_PLLQ << RCC_PLLCFGR_PLLQ_Pos) |
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RCC_PLLCFGR_PLLSRC_HSE // PLLSRC = HSE
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| (DEFAULT_PLLP << RCC_PLLCFGR_PLLP_Pos) |
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(DEFAULT_PLLN << RCC_PLLCFGR_PLLN_Pos) |
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(DEFAULT_PLLM << RCC_PLLCFGR_PLLM_Pos);
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// this will be overriden by static initialization
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SystemCoreClock = DEFAULT_FREQ * 1000000U;
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// enable spread spectrum clock for main PLL
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RCC->SSCGR = RCC_SSCGR_SSCGEN | (44 << RCC_SSCGR_INCSTEP_Pos) |
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(250 << RCC_SSCGR_MODPER_Pos);
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// enable clock security system, HSE clock, and main PLL
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RCC->CR |= RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_PLLON;
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// wait until PLL and HSE ready
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while ((RCC->CR & (RCC_CR_PLLRDY | RCC_CR_HSERDY)) !=
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(RCC_CR_PLLRDY | RCC_CR_HSERDY))
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;
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// APB2=2, APB1=4, AHB=1, system clock = main PLL
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const uint32_t cfgr = RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV4 |
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RCC_CFGR_HPRE_DIV1 | RCC_CFGR_SW_PLL;
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RCC->CFGR = cfgr;
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// wait until PLL is system clock and also verify that the pre-scalers were
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// set
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while (RCC->CFGR != (RCC_CFGR_SWS_PLL | cfgr))
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;
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// turn off the HSI as it is now unused (it will be turned on again
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// automatically if a clock security failure occurs)
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RCC->CR &= ~RCC_CR_HSION;
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// wait until ths HSI is off
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while ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
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;
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// init the TRNG peripheral
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rng_init();
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// set CP10 and CP11 to enable full access to the fpu coprocessor; ARMv7-M
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// Architecture Reference Manual section B3.2.20
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SCB->CPACR |= ((3U << 22) | (3U << 20));
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}
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#ifdef TREZOR_MODEL_T
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void set_core_clock(clock_settings_t settings) {
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/* Enable HSI clock */
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RCC->CR |= RCC_CR_HSION;
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/* Wait till HSI is ready */
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while (!(RCC->CR & RCC_CR_HSIRDY))
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;
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/* Select HSI clock as main clock */
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RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_SW)) | RCC_CFGR_SW_HSI;
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/* Disable PLL */
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RCC->CR &= ~RCC_CR_PLLON;
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/* Set PLL settings */
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clock_conf_t conf = clock_conf[settings];
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RCC->PLLCFGR =
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(RCC_PLLCFGR_RST_VALUE & ~RCC_PLLCFGR_PLLQ & ~RCC_PLLCFGR_PLLSRC &
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~RCC_PLLCFGR_PLLP & ~RCC_PLLCFGR_PLLN & ~RCC_PLLCFGR_PLLM) |
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(conf.pllq << RCC_PLLCFGR_PLLQ_Pos) |
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RCC_PLLCFGR_PLLSRC_HSE // PLLSRC = HSE
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| (conf.pllp << RCC_PLLCFGR_PLLP_Pos) |
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(conf.plln << RCC_PLLCFGR_PLLN_Pos) | (conf.pllm << RCC_PLLCFGR_PLLM_Pos);
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SystemCoreClock = conf.freq * 1000000U;
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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while (!(RCC->CR & RCC_CR_PLLRDY))
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;
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/* Enable PLL as main clock */
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RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_SW)) | RCC_CFGR_SW_PLL;
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HAL_InitTick(TICK_INT_PRIORITY);
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// turn off the HSI as it is now unused (it will be turned on again
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// automatically if a clock security failure occurs)
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RCC->CR &= ~RCC_CR_HSION;
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// wait until ths HSI is off
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while ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
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;
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}
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#endif
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void drop_privileges(void) {
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// jump to unprivileged mode
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// http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/CHDBIBGJ.html
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__asm__ volatile("msr control, %0" ::"r"(0x1));
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__asm__ volatile("isb");
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}
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// from util.s
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extern void shutdown_privileged(void);
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void PVD_IRQHandler(void) {
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TIM1->CCR1 = 0; // turn off display backlight
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shutdown_privileged();
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}
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