mirror of
https://github.com/trezor/trezor-firmware.git
synced 2024-11-14 03:30:02 +00:00
115 lines
3.8 KiB
C
115 lines
3.8 KiB
C
#ifdef SYSTEM_VIEW
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#include "systemview.h"
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#include <stddef.h>
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#include <stdint.h>
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#include <string.h>
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#include "irq.h"
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#include "mpconfigport.h"
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#include "supervise.h"
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#include "SEGGER_SYSVIEW.h"
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#include "SEGGER_SYSVIEW_Conf.h"
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#define SYSTICK ((SYSTICK_REGS *)0xE000E010)
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#define SCS ((SCS_REGS *)0xE000ED00)
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// for storing DWT CYCCNT from SVC call
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volatile uint32_t cyccnt_cycles;
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typedef struct {
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volatile unsigned int CSR;
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volatile unsigned int RVR;
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volatile unsigned int CVR;
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volatile unsigned int CALIB;
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} SYSTICK_REGS;
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typedef struct {
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volatile unsigned int CPUID; // CPUID Base Register
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volatile unsigned int ICSR; // Interrupt Control and State Register
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volatile unsigned int VTOR; // Vector Table Offset Register
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volatile unsigned int
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AIRCR; // Application Interrupt and Reset Control Register
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volatile unsigned int SCR; // System Control Register
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volatile unsigned int CCR; // Configuration and Control Register
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volatile unsigned int SHPR1; // System Handler Priority Register 1
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volatile unsigned int SHPR2; // System Handler Priority Register 2
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volatile unsigned int SHPR3; // System Handler Priority Register 3
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volatile unsigned int SHCSR; // System Handler Control and State Register
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volatile unsigned int CFSR; // Configurable Fault Status Register
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volatile unsigned int HFSR; // HardFault Status Register
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volatile unsigned int DFSR; // Debug Fault Status Register
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volatile unsigned int MMFAR; // MemManage Fault Address Register
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volatile unsigned int BFAR; // BusFault Address Register
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volatile unsigned int AFSR; // Auxiliary Fault Status Register
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volatile unsigned int aDummy0[4]; // 0x40-0x4C Reserved
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volatile unsigned int aDummy1[4]; // 0x50-0x5C Reserved
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volatile unsigned int aDummy2[4]; // 0x60-0x6C Reserved
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volatile unsigned int aDummy3[4]; // 0x70-0x7C Reserved
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volatile unsigned int aDummy4[2]; // 0x80-0x87 - - - Reserved.
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volatile unsigned int CPACR; // Coprocessor Access Control Register
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} SCS_REGS;
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extern uint32_t SystemCoreClock;
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uint32_t svc_get_dwt_cyccnt() {
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if (is_mode_unprivileged()) {
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__asm__ __volatile__("svc %0" ::"i"(SVC_GET_DWT_CYCCNT));
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} else {
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cyccnt_cycles = *DWT_CYCCNT_ADDR;
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}
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return cyccnt_cycles;
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}
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U32 SEGGER_SYSVIEW_X_GetInterruptId() {
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return ((*(U32 *)(0xE000ED04)) & 0x1FF);
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}
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void enable_systemview() {
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SEGGER_SYSVIEW_Conf();
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SEGGER_SYSVIEW_Start();
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U32 v;
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//
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// Configure SysTick and debug monitor interrupt priorities
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// Low value means high priority
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// A maximum of 8 priority bits and a minimum of 3 bits is implemented per
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// interrupt. How many bits are implemented depends on the actual CPU being
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// used If less than 8 bits are supported, the lower bits of the priority byte
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// are RAZ. In order to make sure that priority of monitor and SysTick always
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// differ, please make sure that the difference is visible in the highest 3
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// bits
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v = SCS->SHPR3;
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v |= (0xFFuL << 24); // Lowest prio for SysTick so SystemView does not get
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// interrupted by Systick
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SCS->SHPR3 = v;
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//
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// Configure SysTick interrupt
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// SysTick is running at CPU speed
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// Configure SysTick to fire every ms
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//
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SYSTICK->RVR = (SystemCoreClock / 1000) - 1; // set reload
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SYSTICK->CVR = 0x00; // set counter
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SYSTICK->CSR = 0x07; // enable systick
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}
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#ifdef SYSTEMVIEW_DEST_RTT
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size_t _write(int file, const void *ptr, size_t len);
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#endif
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size_t segger_print(const char *str, size_t len) {
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#ifdef SYSTEMVIEW_DEST_SYSTEMVIEW
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static char str_copy[1024];
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size_t copylen = len > 1023 ? 1023 : len;
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memcpy(str_copy, str, copylen);
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str_copy[copylen] = 0;
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SEGGER_SYSVIEW_Print(str_copy);
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return len;
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#endif
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#ifdef SYSTEMVIEW_DEST_RTT
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_write(0, str, len);
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return len;
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#endif
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}
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#endif
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