cepetr
|
bf119fbee4
|
feat(core): improve display/dma2d syscall verifiers
[no changelog]
|
2025-03-04 08:08:10 +01:00 |
|
cepetr
|
45417bf3bd
|
feat(core): reduce overhead of syscall invocation
[no changelog]
|
2025-03-04 08:08:10 +01:00 |
|
cepetr
|
19ba854c69
|
feat(code): introduce dma2d syscalls
[no changelog]
|
2025-03-04 08:08:10 +01:00 |
|
Martin Milata
|
dadff32f39
|
build(core): use internal model names everywhere
TREZOR_MODEL=T and TREZOR_MODEL=R
no longer work, please use
TREZOR_MODEL=T2T1 and TREZOR_MODEL=T2B1
[no changelog]
|
2025-01-13 16:24:35 +01:00 |
|
tychovrahe
|
0bc729a3da
|
refactor(core): streamline RAM layout
[no changelog]
|
2024-12-11 21:41:52 +01:00 |
|
tychovrahe
|
b0dd521c5d
|
fix(core): separate bootargs from kernel/aux SRAM
[no changelog]
|
2024-11-20 11:17:35 +01:00 |
|
tychovrahe
|
40c5426717
|
fix(core): fix MPU kernel sram setting for STM32U5G
[no changelog]
|
2024-11-20 11:17:35 +01:00 |
|
cepetr
|
089db2cadf
|
refactor(core): restructure embed folder
[no changelog]
|
2024-11-18 09:41:02 +01:00 |
|