17 Commits

Author	SHA1	Message	Date
Ondřej Vejpustek	6fd4739c5c	feat(core): make random delays use chacha_drbg	2021-05-21 13:42:53 +02:00
Ondřej Vejpustek	8ee17f69b3	refactor(core): move wait_random and rdi into separate file	2021-05-21 13:42:53 +02:00
Pavol Rusnak	814db111b2	feat(core): add define to invert display colors on ST7789V	2021-03-10 16:06:18 +01:00
Ondrej Mikle	869cfbbd1c	style(core): style for systemview	2021-01-26 20:53:38 +01:00
Ondrej Mikle	5f837e12b9	feat(core): send messaged through systemview	2021-01-26 20:53:38 +01:00
Ondrej Mikle	c5e986b1ba	feat(core): enable SystemView at firmware start	2021-01-26 20:53:38 +01:00
matejcik	f723dca7b1	core: enable PYSTACK	2020-07-24 14:09:31 +02:00
Ondrej Mikle	33d2bf417b	core: replace bootloader only in production. Fix device for T1 core port JLink upload	2020-07-13 10:45:32 +02:00
Ondřej Vejpustek	c461692f3a	core: implement random delay interrupts	2020-04-16 11:51:28 +02:00
Pavol Rusnak	3de1b3aa54	core/embed: switch to unprivileged in main.c	2020-01-24 12:29:46 +00:00
Jan Pochyla	7deade5a10	core/firmware: PendSV_Handler is defined in pendsv.c	2020-01-07 20:52:43 +01:00
Pavol Rusnak	a9e5149b95	core: reorganize source code to allow boardloader build ... (after DMA changes)	2019-12-15 08:43:00 +00:00
Pavol Rusnak	b34675401c	core/embed: add explicit fault handlers	2019-12-11 16:40:58 +00:00
Pavol Rusnak	c8c27dcd2f	core/embed: enable/disable SDIO/DMA interrupts via supervisor calls	2019-12-11 15:28:49 +00:00
Pavol Rusnak	54d348228f	all: rename TREZOR to Trezor where possible	2019-06-17 20:28:29 +02:00
Andrew Kozlik	f677a0f0db	core: Use PRNG when generating random delays.	2019-06-11 11:41:40 +02:00
matejcik	e5670856a2	MONOREPO CREATE FROM trezor-core	2019-04-15 19:14:40 +02:00