trezor-firmware

Author SHA1 Message Date

Author	SHA1	Message	Date
Jan Pochyla	7c65f0357a	feat(core/rust): Implement exception catching in Rust chore(core): Add test for Rust exc catching chore(core): Document exception catching in Rust [no changelog]	3 years ago
Martin Milata	20fe8552ca	build(core/rust): use correct architecture for T1 TT is Cortex-M4 is Armv7E-M while T1 is Cortex-M3 is Armv7-M: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv6-m-vs-armv7-m---unpacking-the-microcontrollers	3 years ago
Jan Pochyla	6257584951	feat(core): Add Rust bindings to MicroPython and trezorhal core: Remove dangling module decls core: Use new Cargo feature resolver, use external MacOS debug info core: Rust docs improvements core: Upgrade bindgen core: Add test target to Rust ci: build rust sources build(core): .ARM.exidx.text.__aeabi_ui2f in t1 firmware size It's an unwind table for softfloat function inserted by rustc, probably can be removed to save 8 bytes: `599c58db70/link.x.in (L175-L182)` scons: Remove dead code core: Move Rust target to build/rust core: Replace extern with a FFI version core: Add some explanatory Rust comments core: Use correct path for the Rust lib core: Remove Buffer::as_mut() Mutable buffer access needs MP_BUFFER_WRITE flag. TBD in the Protobuf PR. core: Improve docs for micropython::Buffer core: Minor Rust docs changes core: Rewrite trezor_obj_get_ll_checked core: Fix incorrect doc comment core: Remove cc from deps fixup! core: Rewrite trezor_obj_get_ll_checked core: update safety comments	3 years ago

Jan Pochyla

feat(core/rust): Implement exception catching in Rust

chore(core): Add test for Rust exc catching

chore(core): Document exception catching in Rust

[no changelog]

Martin Milata

20fe8552ca

build(core/rust): use correct architecture for T1

TT is Cortex-M4 is Armv7E-M while T1 is Cortex-M3 is Armv7-M:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv6-m-vs-armv7-m---unpacking-the-microcontrollers

Jan Pochyla

6257584951

feat(core): Add Rust bindings to MicroPython and trezorhal

core: Remove dangling module decls

core: Use new Cargo feature resolver, use external MacOS debug info

core: Rust docs improvements

core: Upgrade bindgen

core: Add test target to Rust

ci: build rust sources

build(core): .ARM.exidx.text.__aeabi_ui2f in t1 firmware size

It's an unwind table for softfloat function inserted by rustc, probably
can be removed to save 8 bytes:
599c58db70/link.x.in (L175-L182)

scons: Remove dead code

core: Move Rust target to build/rust

core: Replace extern with a FFI version

core: Add some explanatory Rust comments

core: Use correct path for the Rust lib

core: Remove Buffer::as_mut()

Mutable buffer access needs MP_BUFFER_WRITE flag. TBD in the Protobuf PR.

core: Improve docs for micropython::Buffer

core: Minor Rust docs changes

core: Rewrite trezor_obj_get_ll_checked

core: Fix incorrect doc comment

core: Remove cc from deps

fixup! core: Rewrite trezor_obj_get_ll_checked

core: update safety comments

3 Commits (8abcb6f8ccffa9708df5faec3fc5763834847659)