16 Commits

Author	SHA1	Message	Date
cepetr	bf119fbee4	feat(core): improve display/dma2d syscall verifiers ... [no changelog]	2025-03-04 08:08:10 +01:00
cepetr	8574289493	chore(core): remove unused display function ... [no changelog]	2025-03-04 08:08:10 +01:00
cepetr	19ba854c69	feat(code): introduce dma2d syscalls ... [no changelog]	2025-03-04 08:08:10 +01:00
cepetr	2961f6caf9	refactor(core): improve frame buffer interface ... [no changelog]	2025-03-04 08:08:10 +01:00
tychovrahe	4e74d2852b	refactor(core): extract backlight driver to separate module ... [no changelog]	2025-02-02 22:41:17 +01:00
tychovrahe	8bad0c8675	fix(core): fix flashing old display content on model T ... [no changelog]	2025-01-24 21:59:01 +01:00
tychovrahe	5fd773757c	fix(core): fix fading issues	2025-01-23 15:24:00 +01:00
cepetr	a920b92ad3	fix(core): fix gfx_bitblt initialization ... [no changelog]	2025-01-22 17:21:41 +01:00
tychovrahe	34e033fd4e	fix(core): fix wrong RSOD color on some older Model T devices	2025-01-14 08:21:37 +01:00
cepetr	1f3e640dd9	feat(core): add display_init return value ... [no changelog]	2025-01-14 07:52:15 +01:00
cepetr	27e37de695	fix(core): fix incorrect macro name ... [no changelog]	2025-01-13 19:03:28 +01:00
Martin Milata	dadff32f39	build(core): use internal model names everywhere ... TREZOR_MODEL=T and TREZOR_MODEL=R no longer work, please use TREZOR_MODEL=T2T1 and TREZOR_MODEL=T2B1 [no changelog]	2025-01-13 16:24:35 +01:00
tychovrahe	594445c1f9	fix(core): TS5 - wait for frame to appear on display before raising backlight ... [no changelog]	2025-01-02 11:41:33 +01:00
tychovrahe	dac6c17f73	refactor(core): extract framebuffer queue for reuse ... [no changelog]	2024-12-13 17:24:03 +01:00
tychovrahe	40c5426717	fix(core): fix MPU kernel sram setting for STM32U5G ... [no changelog]	2024-11-20 11:17:35 +01:00
cepetr	089db2cadf	refactor(core): restructure embed folder ... [no changelog]	2024-11-18 09:41:02 +01:00