cepetr
|
6bea09bbe7
|
fix(core): fix firmware hash calculation
[no changelog]
|
2025-06-11 09:46:37 +02:00 |
|
cepetr
|
bbb74c03a4
|
feat(core): introduce secure monitor
[no changelog]
|
2025-06-04 16:58:15 +02:00 |
|
cepetr
|
e66f4f2d83
|
refactor(core): simplify unprivileged SAES execution
[no changelog]
|
2025-06-04 16:58:15 +02:00 |
|
cepetr
|
a133a01a1f
|
feat(core): support mpu region setup per applet
[no changelog]
|
2025-06-04 16:58:15 +02:00 |
|
cepetr
|
1cf9dc4d62
|
refactor(core): simplify linker scripts II
[no changelog]
|
2025-06-04 16:58:15 +02:00 |
|
tychovrahe
|
baa6317113
|
fix(core): fix lockable bootloader logic in secret and MPU
Also, fix firmware build with `DISABLE_OPTIGA=1`.
[no changelog]
|
2025-05-30 19:28:46 +03:00 |
|
tychovrahe
|
7fb272bade
|
chore(core): remove unprivileged SAES on U5G models
[no changelog]
|
2025-05-30 13:12:58 +02:00 |
|
cepetr
|
9df360785e
|
fix(core): fix incorrect constants use
[no changelog]
|
2025-05-12 07:57:46 +02:00 |
|
cepetr
|
adf9872988
|
refactor(core): prevent incomplete mpu driver build
[no changelog]
|
2025-05-12 07:57:46 +02:00 |
|
cepetr
|
7248bf2a48
|
fix(core): fix issue with frame buffer access on D001
[no changelog]
|
2025-04-01 10:00:26 +02:00 |
|
cepetr
|
b5053d9f6e
|
fix(core): add kernel access to assets by default (#4759)
[no changelog]
|
2025-03-11 07:58:57 +01:00 |
|
cepetr
|
bf119fbee4
|
feat(core): improve display/dma2d syscall verifiers
[no changelog]
|
2025-03-04 08:08:10 +01:00 |
|
cepetr
|
45417bf3bd
|
feat(core): reduce overhead of syscall invocation
[no changelog]
|
2025-03-04 08:08:10 +01:00 |
|
cepetr
|
19ba854c69
|
feat(code): introduce dma2d syscalls
[no changelog]
|
2025-03-04 08:08:10 +01:00 |
|
Martin Milata
|
dadff32f39
|
build(core): use internal model names everywhere
TREZOR_MODEL=T and TREZOR_MODEL=R
no longer work, please use
TREZOR_MODEL=T2T1 and TREZOR_MODEL=T2B1
[no changelog]
|
2025-01-13 16:24:35 +01:00 |
|
tychovrahe
|
0bc729a3da
|
refactor(core): streamline RAM layout
[no changelog]
|
2024-12-11 21:41:52 +01:00 |
|
tychovrahe
|
b0dd521c5d
|
fix(core): separate bootargs from kernel/aux SRAM
[no changelog]
|
2024-11-20 11:17:35 +01:00 |
|
tychovrahe
|
40c5426717
|
fix(core): fix MPU kernel sram setting for STM32U5G
[no changelog]
|
2024-11-20 11:17:35 +01:00 |
|
cepetr
|
089db2cadf
|
refactor(core): restructure embed folder
[no changelog]
|
2024-11-18 09:41:02 +01:00 |
|