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@ -90,51 +90,10 @@ void mp_hal_delay_us(mp_uint_t usec) {
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}
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}
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bool sys_tick_has_passed(uint32_t start_tick, uint32_t delay_ms) {
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return HAL_GetTick() - start_tick >= delay_ms;
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}
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// waits until at least delay_ms milliseconds have passed from the sampling of
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// startTick. Handles overflow properly. Assumes stc was taken from
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// HAL_GetTick() some time before calling this function.
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void sys_tick_wait_at_least(uint32_t start_tick, uint32_t delay_ms) {
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while (!sys_tick_has_passed(start_tick, delay_ms)) {
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__WFI(); // enter sleep mode, waiting for interrupt
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}
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}
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mp_uint_t mp_hal_ticks_ms(void) {
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return uwTick;
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}
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// The SysTick timer counts down at 168 MHz, so we can use that knowledge
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// to grab a microsecond counter.
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//
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// We assume that HAL_GetTickis returns milliseconds.
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mp_uint_t mp_hal_ticks_us(void) {
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mp_uint_t irq_state = disable_irq();
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uint32_t counter = SysTick->VAL;
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uint32_t milliseconds = HAL_GetTick();
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uint32_t status = SysTick->CTRL;
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enable_irq(irq_state);
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// It's still possible for the countflag bit to get set if the counter was
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// reloaded between reading VAL and reading CTRL. With interrupts disabled
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// it definitely takes less than 50 HCLK cycles between reading VAL and
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// reading CTRL, so the test (counter > 50) is to cover the case where VAL
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// is +ve and very close to zero, and the COUNTFLAG bit is also set.
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if ((status & SysTick_CTRL_COUNTFLAG_Msk) && counter > 50) {
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// This means that the HW reloaded VAL between the time we read VAL and the
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// time we read CTRL, which implies that there is an interrupt pending
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// to increment the tick counter.
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milliseconds++;
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}
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uint32_t load = SysTick->LOAD;
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counter = load - counter; // Convert from decrementing to incrementing
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// ((load + 1) / 1000) is the number of counts per microsecond.
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//
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// counter / ((load + 1) / 1000) scales from the systick clock to microseconds
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// and is the same thing as (counter * 1000) / (load + 1)
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return milliseconds * 1000 + (counter * 1000) / (load + 1);
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return uwTick * 1000;
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}
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