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@ -1,50 +1,33 @@
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// clang-format off
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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* This file is part of the Trezor project, https://trezor.io/
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*
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* Copyright (c) 2013, 2014 Damien P. George
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* Copyright (c) SatoshiLabs
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef MICROPY_INCLUDED_STM32_IRQ_H
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#define MICROPY_INCLUDED_STM32_IRQ_H
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#ifndef TREZORHAL_IRQ_H
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#define TREZORHAL_IRQ_H
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#include STM32_HAL_H
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#include <stdint.h>
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// Use this macro together with NVIC_SetPriority to indicate that an IRQn is non-negative,
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// which helps the compiler optimise the resulting inline function.
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#define IRQn_NONNEG(pri) ((pri) & 0x7f)
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// these states correspond to values from query_irq, enable_irq and disable_irq
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#define IRQ_STATE_DISABLED (0x00000001)
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#define IRQ_STATE_ENABLED (0x00000000)
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// Enable this to get a count for the number of times each irq handler is called,
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// accessible via pyb.irq_stats().
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// Enables simple IRQ statistics for debugging
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#define IRQ_ENABLE_STATS (0)
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#if IRQ_ENABLE_STATS
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#define IRQ_STATS_MAX (128)
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#define IRQ_STATS_MAX (128)
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extern uint32_t irq_stats[IRQ_STATS_MAX];
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#define IRQ_ENTER(irq) ++irq_stats[irq]
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#define IRQ_EXIT(irq)
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@ -53,111 +36,34 @@ extern uint32_t irq_stats[IRQ_STATS_MAX];
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#define IRQ_EXIT(irq)
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#endif
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static inline uint32_t query_irq(void) {
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return __get_PRIMASK();
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}
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// Checks if interrupts are enabled
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#define IS_IRQ_ENABLED(state) (((state) & 1) == 0)
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static inline void enable_irq(uint32_t state) {
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__set_PRIMASK(state);
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}
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// Get the current value of the CPU's exception mask register.
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// The least significant bit indicates if interrupts are enabled or disabled.
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static inline uint32_t query_irq(void) { return __get_PRIMASK(); }
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// Restore the CPU's exception mask register to a previous state
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static inline void enable_irq(uint32_t state) { __set_PRIMASK(state); }
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// Disable all interrupts and return the current state of the
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// CPU's exception mask register
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static inline uint32_t disable_irq(void) {
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uint32_t state = __get_PRIMASK();
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__disable_irq();
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return state;
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}
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// enable_irq and disable_irq are defined inline in mpconfigport.h
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#if __CORTEX_M >= 0x03
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// irqs with a priority value greater or equal to "pri" will be disabled
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// "pri" should be between 1 and 15 inclusive
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static inline uint32_t raise_irq_pri(uint32_t pri) {
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uint32_t basepri = __get_BASEPRI();
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// If non-zero, the processor does not process any exception with a
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// priority value greater than or equal to BASEPRI.
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// When writing to BASEPRI_MAX the write goes to BASEPRI only if either:
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// - Rn is non-zero and the current BASEPRI value is 0
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// - Rn is non-zero and less than the current BASEPRI value
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pri <<= (8 - __NVIC_PRIO_BITS);
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__ASM volatile ("msr basepri_max, %0" : : "r" (pri) : "memory");
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return basepri;
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}
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// "basepri" should be the value returned from raise_irq_pri
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static inline void restore_irq_pri(uint32_t basepri) {
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__set_BASEPRI(basepri);
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}
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#else
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static inline uint32_t raise_irq_pri(uint32_t pri) {
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return disable_irq();
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}
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// "state" should be the value returned from raise_irq_pri
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static inline void restore_irq_pri(uint32_t state) {
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enable_irq(state);
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}
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#endif
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// IRQ priority definitions.
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//
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// Lower number implies higher interrupt priority.
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//
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// The default priority grouping is set to NVIC_PRIORITYGROUP_4 in the
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// HAL_Init function. This corresponds to 4 bits for the priority field
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// and 0 bits for the sub-priority field (which means that for all intensive
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// purposes that the sub-priorities below are ignored).
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//
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// While a given interrupt is being processed, only higher priority (lower number)
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// interrupts will preempt a given interrupt. If sub-priorities are active
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// then the sub-priority determines the order that pending interrupts of
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// a given priority are executed. This is only meaningful if 2 or more
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// interrupts of the same priority are pending at the same time.
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//
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// The priority of the SysTick timer is determined from the TICK_INT_PRIORITY
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// value which is normally set to 0 in the stm32f4xx_hal_conf.h file.
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//
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// The following interrupts are arranged from highest priority to lowest
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// priority to make it a bit easier to figure out.
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//#def IRQ_PRI_SYSTICK NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 0, 0)
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// The UARTs have no FIFOs, so if they don't get serviced quickly then characters
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// get dropped. The handling for each character only consumes about 0.5 usec
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#define IRQ_PRI_UART NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 1, 0)
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// SDIO must be higher priority than DMA for SDIO DMA transfers to work.
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#define IRQ_PRI_SDIO NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 4, 0)
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// DMA should be higher priority than USB, since USB Mass Storage calls
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// into the sdcard driver which waits for the DMA to complete.
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#define IRQ_PRI_DMA NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 5, 0)
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// Flash IRQ (used for flushing storage cache) must be at the same priority as
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// the USB IRQs, so that the IRQ priority can be raised to this level to disable
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// both the USB and cache flushing, when storage transfers are in progress.
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#define IRQ_PRI_FLASH NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0)
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#define IRQ_PRI_OTG_FS NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0)
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#define IRQ_PRI_OTG_HS NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0)
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#define IRQ_PRI_TIM5 NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0)
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#define IRQ_PRI_CAN NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 7, 0)
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#define IRQ_PRI_SPI NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 8, 0)
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// Interrupt priority for non-special timers.
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#define IRQ_PRI_TIMX NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 13, 0)
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// IRQ priority levels used throughout the system
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#define IRQ_PRI_EXTINT NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 14, 0)
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// Highest priority in the system (only RESET, NMI, and
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// HardFault can preempt exceptions at this priority level)
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#define IRQ_PRI_HIGHEST NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 0, 0)
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//?#define IRQ_PRI_RTC_WKUP NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 15, 0)
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// Standard priority for common interrupt handlers
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#define IRQ_PRI_NORMAL NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 8, 0)
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// !@# TAMPER interrupt priority should be probably much higher
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#define IRQ_PRI_TAMP NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 15, 0)
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// Lowest priority in the system used by SVC and PENDSV exception handlers
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#define IRQ_PRI_LOWEST NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 15, 0)
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#endif // MICROPY_INCLUDED_STM32_IRQ_H
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#endif // TREZORHAL_IRQ_H
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cepetr
3 months ago