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https://github.com/trezor/trezor-firmware.git
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core/embed/usb: add back usb fs code for t1 and redo fifo sizing
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6137a55b06
commit
e3539b0a73
@ -407,16 +407,49 @@ void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
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*/
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USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev)
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{
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#if defined(USE_USB_FS)
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// Trezor 1 uses the OTG_FS peripheral
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if (pdev->id == USB_PHY_FS_ID) {
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/*Set LL Driver parameters */
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pcd_fs_handle.Instance = USB_OTG_FS;
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pcd_fs_handle.Init.dev_endpoints = 4;
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pcd_fs_handle.Init.use_dedicated_ep1 = 0;
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pcd_fs_handle.Init.ep0_mps = 0x40;
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pcd_fs_handle.Init.dma_enable = 0;
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pcd_fs_handle.Init.low_power_enable = 0;
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pcd_fs_handle.Init.phy_itface = PCD_PHY_EMBEDDED;
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pcd_fs_handle.Init.Sof_enable = 1;
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pcd_fs_handle.Init.speed = PCD_SPEED_FULL;
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pcd_fs_handle.Init.vbus_sensing_enable = 0; // No VBUS Sensing on USB0
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/* Link The driver to the stack */
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pcd_fs_handle.pData = pdev;
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pdev->pData = &pcd_fs_handle;
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/*Initialize LL Driver */
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HAL_PCD_Init(&pcd_fs_handle);
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// the OTG_FS peripheral has a dedicated 1.25KiB data RAM from which we
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// allocate an area for each transmit FIFO and the single shared receive FIFO.
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// the configuration is in terms of 32-bit words, so we have 320 32-bit words
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// in this dedicated 1.25KiB data RAM to use. see section 6.3.8 in UM1021 and 29.13 in RM0033.
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// USB packets that we deal with are 64 bytes in size which equates to 16 32-bit words.
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// we size the transmit FIFO's equally and give the rest of the space to the receive FIFO.
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const uint16_t transmit_fifo_size = 48; // 48 = 16 * 3 meaning that we give 3 packets of space for each transmit fifo
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const uint16_t receive_fifo_zie = 128; // 128 = 320 - 4 * 48
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HAL_PCDEx_SetRxFiFo(&pcd_fs_handle, receive_fifo_zie);
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for (uint16_t i = 0; i < 4; i++) {
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HAL_PCDEx_SetTxFiFo(&pcd_fs_handle, i, transmit_fifo_size);
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}
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}
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#endif
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#if defined(USE_USB_HS_IN_FS)
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// Trezor T uses the OTG_HS peripheral
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if (pdev->id == USB_PHY_HS_ID) {
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/* Set LL Driver parameters */
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pcd_hs_handle.Instance = USB_OTG_HS;
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pcd_hs_handle.Init.dev_endpoints = 6;
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pcd_hs_handle.Init.use_dedicated_ep1 = 0;
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pcd_hs_handle.Init.ep0_mps = 0x40;
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pcd_hs_handle.Init.dma_enable = 0;
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pcd_hs_handle.Init.low_power_enable = 0;
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pcd_hs_handle.Init.phy_itface = PCD_PHY_EMBEDDED;
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pcd_hs_handle.Init.Sof_enable = 1;
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pcd_hs_handle.Init.speed = PCD_SPEED_HIGH_IN_FULL;
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@ -429,7 +462,6 @@ USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev)
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pdev->pData = &pcd_hs_handle;
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/* Initialize LL Driver */
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HAL_PCD_Init(&pcd_hs_handle);
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// the OTG_HS peripheral has a dedicated 4KiB data RAM from which we
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// allocate an area for each transmit FIFO and the single shared receive FIFO.
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// the configuration is in terms of 32-bit words, so we have 1024 32-bit words
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@ -445,6 +477,7 @@ USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev)
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HAL_PCDEx_SetTxFiFo(&pcd_hs_handle, i, transmit_fifo_size);
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}
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}
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#endif
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return USBD_OK;
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}
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