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fix(core): fix memory layout on u5

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This commit is contained in:
cepetr 2024-10-02 12:07:26 +02:00 committed by cepetr
parent 976867d7d8
commit d80e8c26f5
3 changed files with 18 additions and 16 deletions
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2
core/embed/trezorhal/stm32u5/linker/u58/firmware.ld
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@ -6,7 +6,7 @@ MEMORY {
FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = FIRMWARE_MAXSIZE FLASH (rx) : ORIGIN = KERNEL_START, LENGTH = FIRMWARE_MAXSIZE
SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - KERNEL_SRAM1_SIZE SRAM1 (wal) : ORIGIN = MCU_SRAM1, LENGTH = MCU_SRAM1_SIZE - KERNEL_SRAM1_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2 + KERNEL_SRAM2_SIZE, LENGTH = MCU_SRAM2_SIZE - KERNEL_SRAM2_SIZE SRAM2 (wal) : ORIGIN = MCU_SRAM2 + KERNEL_SRAM2_SIZE, LENGTH = MCU_SRAM2_SIZE - KERNEL_SRAM2_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3 + KERNEL_SRAM3_SIZE, LENGTH = MCU_SRAM3_SIZE - KERNEL_SRAM3_SIZE SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = MCU_SRAM3_SIZE - KERNEL_SRAM3_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = 0K /* SRAM5 is not available */ SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = 0K /* SRAM5 is not available */
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = 0K /* SRAM6 is not available */ SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = 0K /* SRAM6 is not available */
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = 0K /* not allocated to coreapp */ SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = 0K /* not allocated to coreapp */

16
core/embed/trezorhal/stm32u5/linker/u58/kernel.ld
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@ -8,7 +8,7 @@ MEMORY {
BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE BOOT_ARGS (wal) : ORIGIN = MCU_SRAM2 - BOOTARGS_SIZE, LENGTH = BOOTARGS_SIZE
SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = KERNEL_SRAM2_SIZE - KERNEL_U_RAM_SIZE SRAM2 (wal) : ORIGIN = MCU_SRAM2, LENGTH = KERNEL_SRAM2_SIZE - KERNEL_U_RAM_SIZE
SRAM2_U (wal) : ORIGIN = MCU_SRAM2 + KERNEL_SRAM2_SIZE - KERNEL_U_RAM_SIZE, LENGTH = KERNEL_U_RAM_SIZE SRAM2_U (wal) : ORIGIN = MCU_SRAM2 + KERNEL_SRAM2_SIZE - KERNEL_U_RAM_SIZE, LENGTH = KERNEL_U_RAM_SIZE
SRAM3 (wal) : ORIGIN = MCU_SRAM3, LENGTH = KERNEL_SRAM3_SIZE SRAM3 (wal) : ORIGIN = MCU_SRAM3 + MCU_SRAM3_SIZE - KERNEL_SRAM3_SIZE, LENGTH = KERNEL_SRAM3_SIZE
SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = 0K /* SRAM5 is not available */ SRAM5 (wal) : ORIGIN = MCU_SRAM5, LENGTH = 0K /* SRAM5 is not available */
SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = 0K /* SRAM6 is not available */ SRAM6 (wal) : ORIGIN = MCU_SRAM6, LENGTH = 0K /* SRAM6 is not available */
SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE SRAM4 (wal) : ORIGIN = MCU_SRAM4, LENGTH = MCU_SRAM4_SIZE
@ -61,10 +61,10 @@ _shutdown_clear_ram_3_start = 0;
_shutdown_clear_ram_3_end = 0; _shutdown_clear_ram_3_end = 0;
/* used by applet cleaning code */ /* used by applet cleaning code */
_coreapp_clear_ram_0_start = MCU_SRAM2 + KERNEL_SRAM2_SIZE; _coreapp_clear_ram_0_start = MCU_SRAM1;
_coreapp_clear_ram_0_size = MCU_SRAM2_SIZE - KERNEL_SRAM2_SIZE; _coreapp_clear_ram_0_size = MCU_SRAM1_SIZE - KERNEL_SRAM1_SIZE;
_coreapp_clear_ram_1_start = MCU_SRAM3 + KERNEL_SRAM3_SIZE; _coreapp_clear_ram_1_start = MCU_SRAM2 + KERNEL_SRAM2_SIZE;
_coreapp_clear_ram_1_size = MCU_SRAM3_SIZE - KERNEL_SRAM3_SIZE; _coreapp_clear_ram_1_size = MCU_SRAM2_SIZE - KERNEL_SRAM2_SIZE + MCU_SRAM3_SIZE - KERNEL_SRAM3_SIZE;
sram_u_start = ORIGIN(SRAM2_U); sram_u_start = ORIGIN(SRAM2_U);
sram_u_end = ORIGIN(SRAM2_U) + LENGTH(SRAM2_U); sram_u_end = ORIGIN(SRAM2_U) + LENGTH(SRAM2_U);
@ -113,6 +113,7 @@ SECTIONS {
.bss : ALIGN(4) { .bss : ALIGN(4) {
*(.no_dma_buffers*); *(.no_dma_buffers*);
*(.buf*);
*(.bss*); *(.bss*);
. = ALIGN(4); . = ALIGN(4);
} >SRAM1 } >SRAM1
@ -147,11 +148,6 @@ SECTIONS {
. = ALIGN(4); . = ALIGN(4);
} >SRAM3 } >SRAM3
.buf : ALIGN(4) {
*(.buf*);
. = ALIGN(4);
} >SRAM3
.boot_args : ALIGN(8) { .boot_args : ALIGN(8) {
*(.boot_command*); *(.boot_command*);

16
core/embed/trezorhal/stm32u5/mpu.c
View File

@ -126,11 +126,16 @@ static void mpu_set_attributes(void) {
#endif #endif
#ifdef STM32U585xx #ifdef STM32U585xx
#define GRAPHICS_START FMC_BANK1 // Two frame buffers at the end of SRAM3
#define GRAPHICS_SIZE SIZE_16M #define GRAPHICS_START (SRAM3_BASE + SRAM3_SIZE - KERNEL_SRAM3_SIZE)
#define GRAPHICS_SIZE KERNEL_SRAM3_SIZE
// Extended peripheral block to cover FMC1 that's used for display
// 512M of periherals + 16M for FMC1 area that follows
#define PERIPH_SIZE (SIZE_512M + SIZE_16M)
#else #else
#define GRAPHICS_START GFXMMU_VIRTUAL_BUFFERS_BASE #define GRAPHICS_START GFXMMU_VIRTUAL_BUFFERS_BASE
#define GRAPHICS_SIZE SIZE_16M #define GRAPHICS_SIZE SIZE_16M
#define PERIPH_SIZE SIZE_512M
#endif #endif
#define OTP_AND_ID_SIZE 0x800 #define OTP_AND_ID_SIZE 0x800
@ -175,7 +180,8 @@ extern uint32_t _codelen;
#define COREAPP_RAM1_SIZE (SRAM1_SIZE - KERNEL_SRAM1_SIZE) #define COREAPP_RAM1_SIZE (SRAM1_SIZE - KERNEL_SRAM1_SIZE)
#define COREAPP_RAM2_START (SRAM2_BASE + KERNEL_SRAM2_SIZE) #define COREAPP_RAM2_START (SRAM2_BASE + KERNEL_SRAM2_SIZE)
#define COREAPP_RAM2_SIZE (SRAM_SIZE - (SRAM1_SIZE + KERNEL_SRAM2_SIZE)) #define COREAPP_RAM2_SIZE \
(SRAM2_SIZE - KERNEL_SRAM2_SIZE + SRAM3_SIZE - KERNEL_SRAM3_SIZE)
#else #else
#define COREAPP_RAM1_START SRAM5_BASE #define COREAPP_RAM1_START SRAM5_BASE
#define COREAPP_RAM1_SIZE SRAM5_SIZE #define COREAPP_RAM1_SIZE SRAM5_SIZE
@ -299,7 +305,7 @@ mpu_mode_t mpu_reconfig(mpu_mode_t mode) {
// clang-format off // clang-format off
switch (mode) { switch (mode) {
case MPU_MODE_SAES: case MPU_MODE_SAES:
SET_REGION( 5, PERIPH_BASE_NS, SIZE_512M, PERIPHERAL, YES, YES ); // Peripherals - SAES, TAMP SET_REGION( 5, PERIPH_BASE_NS, PERIPH_SIZE, PERIPHERAL, YES, YES ); // Peripherals - SAES, TAMP
break; break;
default: default:
SET_REGION( 5, GRAPHICS_START, GRAPHICS_SIZE, SRAM, YES, YES ); // Frame buffer or display interface SET_REGION( 5, GRAPHICS_START, GRAPHICS_SIZE, SRAM, YES, YES ); // Frame buffer or display interface
@ -362,7 +368,7 @@ mpu_mode_t mpu_reconfig(mpu_mode_t mode) {
break; break;
default: default:
// All peripherals (Privileged, Read-Write, Non-Executable) // All peripherals (Privileged, Read-Write, Non-Executable)
SET_REGION( 7, PERIPH_BASE_NS, SIZE_512M, PERIPHERAL, YES, NO ); SET_REGION( 7, PERIPH_BASE_NS, PERIPH_SIZE, PERIPHERAL, YES, NO );
break; break;
} }
// clang-format on // clang-format on