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build(core): move default values for bindgen macros (back) into build.rs

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matejcik 2024-05-17 12:12:35 +02:00 committed by matejcik
parent 751390ec08
commit cf58fdd313
2 changed files with 50 additions and 17 deletions
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6
core/Makefile
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@ -43,8 +43,6 @@ OPENOCD_INTERFACE ?= stlink
# OpenOCD transport default. Alternative: jtag
OPENOCD_TRANSPORT ?= hla_swd
BINDGEN_MACROS_COMMON=-I../unix,-I../trezorhal/unix,-I../../build/unix,-I../../vendor/micropython/ports/unix,-I../../../crypto,-I../../../storage,-I../../vendor/micropython,-I../../vendor/micropython/lib/uzlib,-I../lib,-I../trezorhal,-I../trezorhal/unix,-I../models,-DTREZOR_EMULATOR,-DTREZOR_BOARD="boards/board-unix.h",
ifeq ($(TREZOR_MODEL), 1)
MCU = STM32F2
LAYOUT_FILE = embed/models/model_T1B1.h
@ -53,13 +51,11 @@ else ifeq ($(TREZOR_MODEL),$(filter $(TREZOR_MODEL),T))
MCU = STM32F4
LAYOUT_FILE = embed/models/model_T2T1.h
OPENOCD_TARGET = target/stm32f4x.cfg
BINDGEN_MACROS_MODEL = -DSTM32F427,-DTREZOR_MODEL_T,-DFLASH_BIT_ACCESS=1,-DFLASH_BLOCK_WORDS=1,
MODEL_FEATURE = model_tt
else ifeq ($(TREZOR_MODEL),$(filter $(TREZOR_MODEL),R))
MCU = STM32F4
LAYOUT_FILE = embed/models/model_T2B1.h
OPENOCD_TARGET = target/stm32f4x.cfg
BINDGEN_MACROS_MODEL =-DSTM32F427,-DTREZOR_MODEL_R,-DFLASH_BIT_ACCESS=1,-DFLASH_BLOCK_WORDS=1,
MODEL_FEATURE = model_tr
else ifeq ($(TREZOR_MODEL),$(filter $(TREZOR_MODEL),T3T1))
MCU = STM32U5
@ -144,7 +140,6 @@ emu: ## run emulator
test: ## run unit tests
cd tests ; ./run_tests.sh $(TESTOPTS)
test_rust: export BINDGEN_MACROS=$(BINDGEN_MACROS_COMMON)$(BINDGEN_MACROS_MODEL)
test_rust: ## run rs unit tests
cd embed/rust ; cargo test $(TESTOPTS) --target=$(RUST_TARGET) \
--no-default-features --features $(MODEL_FEATURE),test \
@ -214,7 +209,6 @@ typecheck: pyright
pyright:
python ../tools/pyright_tool.py
clippy: export BINDGEN_MACROS:=$(BINDGEN_MACROS_COMMON)$(BINDGEN_MACROS_MODEL)
clippy:
cd embed/rust ; cargo clippy $(TESTOPTS) --all-features --target=$(RUST_TARGET)

61
core/embed/rust/build.rs
View File

@ -14,12 +14,54 @@ fn main() {
link_core_objects();
}
// fn block_words() -> String {
// match env::var("FLASH_BLOCK_WORDS") {
// Ok(model) => model,
// Err(_) => panic!("FLASH_BLOCK_WORDS not set")
// }
// }
const DEFAULT_BINDGEN_MACROS_COMMON: &[&str] = &[
"-I../unix",
"-I../trezorhal/unix",
"-I../../build/unix",
"-I../../vendor/micropython/ports/unix",
"-I../../../crypto",
"-I../../../storage",
"-I../../vendor/micropython",
"-I../../vendor/micropython/lib/uzlib",
"-I../lib",
"-I../trezorhal",
"-I../trezorhal/unix",
"-I../models",
"-DTREZOR_EMULATOR",
"-DTREZOR_BOARD=\"boards/board-unix.h\"",
];
#[cfg(feature = "model_tt")]
const DEFAULT_BINDGEN_MACROS_T2T1: &[&str] = &[
"-DSTM32F427",
"-DTREZOR_MODEL_T",
"-DFLASH_BIT_ACCESS=1",
"-DFLASH_BLOCK_WORDS=1",
];
#[cfg(not(feature = "model_tt"))]
const DEFAULT_BINDGEN_MACROS_T2T1: &[&str] = &[];
#[cfg(feature = "model_tr")]
const DEFAULT_BINDGEN_MACROS_T2B1: &[&str] = &[
"-DSTM32F427",
"-DTREZOR_MODEL_R",
"-DFLASH_BIT_ACCESS=1",
"-DFLASH_BLOCK_WORDS=1",
];
#[cfg(not(feature = "model_tr"))]
const DEFAULT_BINDGEN_MACROS_T2B1: &[&str] = &[];
fn add_bindgen_macros<'a>(clang_args: &mut Vec<&'a str>, envvar: Option<&'a str>) {
let default_macros = DEFAULT_BINDGEN_MACROS_COMMON
.iter()
.chain(DEFAULT_BINDGEN_MACROS_T2T1)
.chain(DEFAULT_BINDGEN_MACROS_T2B1);
match envvar {
Some(envvar) => clang_args.extend(envvar.split(',')),
None => clang_args.extend(default_macros),
}
}
/// Generates Rust module that exports QSTR constants used in firmware.
#[cfg(feature = "micropython")]
@ -70,12 +112,9 @@ fn prepare_bindings() -> bindgen::Builder {
let mut bindings = bindgen::Builder::default();
let mut clang_args: Vec<&str> = Vec::new();
let includes = env::var("BINDGEN_MACROS").unwrap();
let args = includes.split(',');
for arg in args {
clang_args.push(arg);
}
let bindgen_macros_env = env::var("BINDGEN_MACROS").ok();
add_bindgen_macros(&mut clang_args, bindgen_macros_env.as_deref());
#[cfg(feature = "xframebuffer")]
{