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T2W1

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tychovrahe 2025-03-06 11:25:43 +01:00
parent 864d7e62d9
commit cae275ee5b
2 changed files with 5 additions and 5 deletions
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4
core/embed/models/T2W1/memory.ld
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@ -52,8 +52,6 @@ S_MAIN_RAM_START = 0x10004000;
S_MAIN_RAM_SIZE = 0xbf00;
K_MAIN_STACK_START = 0x10000000;
K_MAIN_STACK_SIZE = 0x2000;
K_AUX2_RAM_START = 0x10002000;
K_AUX2_RAM_SIZE = 0xa000;
K_FB1_RAM_START = 0x1000c000;
K_FB1_RAM_SIZE = 0x0;
K_MAIN_RAM_START = 0x1000c000;
@ -64,5 +62,7 @@ DMABUF_RAM_START = 0x20000000;
DMABUF_RAM_SIZE = 0x800;
AUX1_RAM_START = 0x20000800;
AUX1_RAM_SIZE = 0x2f800;
AUX2_RAM_START = 0x10002000;
AUX2_RAM_SIZE = 0xa000;
CODE_ALIGNMENT = 0x200;
COREAPP_ALIGNMENT = 0x200;

6
core/embed/models/T2W1/model_T2W1.h
View File

@ -102,9 +102,6 @@
#define K_MAIN_STACK_START 0x10000000
#define K_MAIN_STACK_SIZE (8 * 1024)
#define K_AUX2_RAM_START 0x10002000
#define K_AUX2_RAM_SIZE (40 * 1024)
#define K_FB1_RAM_START 0x1000C000
#define K_FB1_RAM_SIZE (0)
@ -121,6 +118,9 @@
#define AUX1_RAM_START (0x20000800)
#define AUX1_RAM_SIZE (190 * 1024)
#define AUX2_RAM_START 0x10002000
#define AUX2_RAM_SIZE (40 * 1024)
// misc
#define CODE_ALIGNMENT 0x200
#define COREAPP_ALIGNMENT 0x200