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fix(core): fix clock setting on U5 for 32 MHz HSE
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@ -31,18 +31,11 @@ const uint32_t MSIRangeTable[16] = {48000000U, 24000000U, 16000000U, 12000000U,
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4000000U, 2000000U, 1330000U, 1000000U,
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4000000U, 2000000U, 1330000U, 1000000U,
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3072000U, 1536000U, 1024000U, 768000U,
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3072000U, 1536000U, 1024000U, 768000U,
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400000U, 200000U, 133000U, 100000U};
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400000U, 200000U, 133000U, 100000U};
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typedef struct {
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uint32_t freq;
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uint32_t pllq;
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uint32_t pllp;
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uint32_t pllm;
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uint32_t plln;
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} clock_conf_t;
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// PLLCLK = ((HSE / PLLM) * PLLN) / PLLR
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// PLLCLK = ((HSE / PLLM) * PLLN) / PLLR
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#ifdef HSE_32MHZ
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#ifdef HSE_32MHZ
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#define PLLM_COEF 2U
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#define PLLM_COEF 2U
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#define PLLN_COEF 1U
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#define PLLN_COEF 2U
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#elif defined HSE_16MHZ
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#elif defined HSE_16MHZ
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#define PLLM_COEF 1U
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#define PLLM_COEF 1U
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#define PLLN_COEF 2U
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#define PLLN_COEF 2U
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@ -56,31 +49,15 @@ typedef struct {
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#define PLLN_COEF 2U
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#define PLLN_COEF 2U
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#endif
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#endif
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#if defined STM32U5
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#define DEFAULT_FREQ 160U
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#define DEFAULT_FREQ 160U
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#define DEFAULT_PLLM PLLM_COEF
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#define DEFAULT_PLLM PLLM_COEF
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#define DEFAULT_PLLN (5 * PLLN_COEF) // mult by x
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#define DEFAULT_PLLN (5 * PLLN_COEF) // mult by x
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#define DEFAULT_PLLR 1U // division by 1
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#define DEFAULT_PLLR 1U // division by 1
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#define DEFAULT_PLLQ 1U // division by 1
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#define DEFAULT_PLLQ 1U // division by 1
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#define DEFAULT_PLLP 5U // division by 5
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#define DEFAULT_PLLP 5U // division by 5
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#else
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#error Unsupported MCU
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#endif
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uint32_t SystemCoreClock = DEFAULT_FREQ * 1000000U;
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uint32_t SystemCoreClock = DEFAULT_FREQ * 1000000U;
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// assuming HSE 16 MHz
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clock_conf_t clock_conf[1] = {
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{
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// clk = ((16MHz / 1) * 10) / 1 = 160 MHz
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.freq = 160,
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.pllp = 1,
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.pllq = PLLM_COEF,
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.pllm = 1,
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.plln = 5 * PLLN_COEF,
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},
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};
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#pragma GCC optimize( \
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#pragma GCC optimize( \
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"no-stack-protector") // applies to all functions in this file
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"no-stack-protector") // applies to all functions in this file
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