feat(core): use HSI as PLL source on T3T1

[no changelog]

core/embed/trezorhal/boards/Clocks_T3T1_revE.md

@@ -0,0 +1,36 @@
+# STM32U5 Clock Configuration for T3T1, rev E.
+
+## Overview
+
+No HSE nor LSE is used.
+
+We use 16 MHz HSI as PLL source.
+
+160 MHz PLLCLK is used as system clock SYSCLK, which is not divided further, so HCLK is also 160 MHz.
+
+APB1, APB2 and APB3 are also not divided, so PCLK1, PCLK2 and PCLK3 are all 160 MHz
+
+CLK48 is derived from HSI48, which is 48 MHz.
+
+## Peripherals
+
+### USB FS
+USB FS is clocked from CLK48, and CRS is used for clock synchronization.
+
+### RNG
+RNG is clocked from CLK48.
+
+### SDMMC
+SDMMC is clocked from CLK48.
+
+### I2C1
+I2C1 is clocked from PCLK1, 160 MHz
+
+### I2C2
+I2C2 is clocked from PCLK1, 160 MHz
+
+### I2C3
+I2C3 is clocked from PCLK3, 160 MHz
+
+### SAES
+SAES is clocked from SHSI, 48 MHz

core/embed/trezorhal/boards/trezor_t3t1_revE.h

@@ -5,7 +5,6 @@
 #define DISPLAY_RESY 240
 
 #define VDD_1V8 1
-#define HSE_16MHZ 1
 
 #define USE_SD_CARD 1
 #define USE_I2C 1

core/embed/trezorhal/stm32f4/usbd_conf.c

@@ -130,6 +130,20 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
     HAL_PWREx_EnableVddUSB();
     __HAL_RCC_PWR_CLK_DISABLE();
 
+
+    RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+    /** Enable the SYSCFG APB clock */
+    __HAL_RCC_CRS_CLK_ENABLE();
+
+    /** Configures CRS */
+    RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+    RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+    RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+    RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
+    RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+    RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+    HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
 #endif
 
     /* Set USBFS Interrupt priority */

core/embed/trezorhal/stm32u5/platform.c

@@ -57,7 +57,9 @@ uint32_t SystemCoreClock = DEFAULT_FREQ * 1000000U;
 #elif defined HSE_8MHZ
 #define PLLN_COEF 2U
 #else
-#error Unsupported HSE frequency
+// no HSE available, use 16MHz HSI
+#define HSI_ONLY
+#define PLLN_COEF 1U
 #endif
 
 // assuming HSE 16 MHz
@@ -115,12 +117,21 @@ void SystemInit(void) {
   while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY))
     ;
 
+#ifndef HSI_ONLY
   __HAL_RCC_HSE_CONFIG(RCC_HSE_ON);
   while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
     ;
-
   __HAL_RCC_PLL_CONFIG(RCC_PLLSOURCE_HSE, RCC_PLLMBOOST_DIV1, DEFAULT_PLLM,
                        DEFAULT_PLLN, DEFAULT_PLLP, DEFAULT_PLLQ, DEFAULT_PLLR);
+#else
+  RCC->CR |= RCC_CR_HSION;
+  // wait until the HSI is on
+  while ((RCC->CR & RCC_CR_HSION) != RCC_CR_HSION)
+    ;
+
+  __HAL_RCC_PLL_CONFIG(RCC_PLLSOURCE_HSI, RCC_PLLMBOOST_DIV1, DEFAULT_PLLM,
+                       DEFAULT_PLLN, DEFAULT_PLLP, DEFAULT_PLLQ, DEFAULT_PLLR);
+#endif
 
   __HAL_RCC_PLL_FRACN_DISABLE();
 
@@ -170,15 +181,17 @@ void SystemInit(void) {
   // this will be overriden by static initialization
   SystemCoreClock = DEFAULT_FREQ * 1000000U;
 
-  // enable clock security system, HSE clock, and main PLL
+#ifndef HSI_ONLY
+  // enable clock security system
   RCC->CR |= RCC_CR_CSSON;
 
   // turn off the HSI as it is now unused (it will be turned on again
   // automatically if a clock security failure occurs)
   RCC->CR &= ~RCC_CR_HSION;
-  // wait until ths HSI is off
+  // wait until the HSI is off
   while ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
     ;
+#endif
 
   // TODO turn off MSI?